09-25-2020 07:24 AM
I would like to capture using Fragmented Frame buffer using FrameBuffer WR or VDMA or any other possible Xilinx XP? I mean to say, Let say 1920x1080 (4bpp) resolution frame divide into 4 section and want to save in 4 different area of memory. lets say 1920x 256 pixel on memory arear 1 , second part 1920x256 pixel on Memory area2.......so on....... till complete one 1920x1080 resolution frame.
I have already tried with FrameBuffer WR IP and no success with it as its only work on continuous memory Frame buffer.
Is there anyway to achieve this requirement directly with support from IP?
Does VDMA IP support this functionality? I can see total 16/32 Strat address supported but not sure does it support like this.
From Linux V4L2 layer, you can use something like this: (multiplanar section)
09-28-2020 07:58 AM - edited 09-28-2020 07:59 AM
This function can be implemented very easily in HLS, by changing the memory write addresses in your loop.
If you haven't used HLS, I recommend you go through all the tutorials first, it can be quite aggravating, but it is worth it once you figure out the idiosyncrasies.
09-28-2020 08:11 AM - edited 09-28-2020 08:20 AM
@reaiken I am not sure what you are referring. can you point me how can you do by changing memory write addresses in loop? which driver suppose to be change?
I am using Petalinux 2019.2. please explain little bit more. I will have a look HLS meanwhile.
09-28-2020 08:37 AM - edited 09-28-2020 08:45 AM
I was referring to writing a custom IP block using Vivado HLS.
Basically, you write the program in C or C++, and you can configure it for AXI4-Stream input and a memory-mapped output.
Since you are controlling where you write to memory in your C program, you can change the addresses in your program on-the-fly, to write the first portion to one section of memory, the next to another, and so forth.
You could also configure it to generate an interrupt on completion of a portion of the incoming stream frame, and dynamically change the address to the next memory section. and repeat this until the entire frame is complete.
Basically, you would be writing your own custom VDMA IP block to use in Vivado, but with the features you want. HLS automatically generates the SW driver with all the setup and interrupt functions for each of your control variables.
As I said, it will take some time to learn it and get used to using C to program hardware. Hint: you can't think of it as "normal" C or "normal" hardware, it is a strange mix of both that will occasionally drive you to drinking. Check out the excellent video tutorials posted by @florentw in the Xilinx Video Series at the top of this forum. There are a few on using HLS to generate a video crop function and a pattern generator.
Sorry, I can't help you with Petalinux, I'm a bare-metal kind of guy.
09-28-2020 08:47 AM - edited 09-28-2020 08:48 AM
Thank you for an excellent explanation. I will definitely try to see option with HLS.
Unfortunately, I have to use Petalinux in project so if I cant control from V4L2 layer than I cant use HLS based custom IP as my System is very complex and connected with many external ML/CNN Compression processor so I must need Linux OS layer to run.
I will have a look this option and see if I can hack around driver to work with Linux or existing Xilinx VDMA driver.