04-23-2019 12:55 PM - edited 04-23-2019 02:13 PM
I have a camera routed to a MIPI CSI-2 RX block, which in turn is routed to a VDMA and then the processor. I'm using a ZynqMP UltraScale chip. When I initialize the camera I see the packet count registers in the MIPI D-PHY core of the MIPI CSI-2 RX block incrementing and then wrapping, but when I configure the VDMA from Linux and start capturing I don't see the S2MM IRQ Frame count increase to more than 2. I also don't see any data being sent between the MIPI CSI2 RX block and the VDMA using a ILA and trying to trigger on TVALID.
I've attached another ILA and read the following pins of the MIPI CSI-2 RX block:
I've attached a asciinema recording which continously prints select registers from the aforementioned IP as I try to run the VDMA. Play the recording using:
asciinema play 1556046907-camera-debug.asciinema.txt
I could use some help debugging why I don't see any frames being sent from the MIPI CSI-2 to the VDMA.
I also noticed there are either "!" or "?" marks on all the ports of the MIPI CSI-2 block. I'm not sure how to interpret those and couldn't find any information about them.
04-30-2019 02:04 PM
05-01-2019 02:29 PM
05-02-2019 08:35 AM
05-02-2019 08:41 AM
# ./debug.sh MIPI CSI-2 RX Controller Core Registers @ 0xa0000000 Core Configuration ENABLED Interrupt Status STOP Clock Lane Information STOP Lane 0 Information STOP Lane 1 Information STOP Lane 2 Information STOP Lane 3 Information STOP MIPI D-PHY Core Registers @ 0xa0010000 Control ENABLED 0x2 Initialization timer 100000 ns Clock lane status 0x18 Data Lane 0 Status INITIALIZED STOP Packet count: 51128 Data Lane 1 Status INITIALIZED STOP Packet count: 0 Data Lane 2 Status INITIALIZED STOP Packet count: 29468 Data Lane 3 Status INITIALIZED STOP Packet count: 29468 High-speed 0 settle 145 ns High-speed 1 settle 145 ns High-speed 2 settle 145 ns High-speed 4 settle 145 ns AXI VDMA Register Space @ 0xa0020000 S2MM Control RUN CIRCULAR IRQFRAMECOUNT IRQ Frame #: 0 IRQ Delay #: 2 S2MM Status RUN IRQ Frame #: 0 IRQ Delay #: 2 Vertical size Lines of data: 1080 Horizontal size Size of data: 0 Enable vert flip ENABLE
05-02-2019 11:22 AM
We were able to synthesize a new bitstream for the ZCU102 and capture data in Linux. One important distinction is that on our board (as I referenced above) data lane 0 seems to be receiving twice the number of packets, while 1 does not receive any. The remaining lanes appear to behave normally.
05-03-2019 02:21 PM