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Observer
Observer
1,380 Views
Registered: ‎06-28-2018

Frames not being sent from MIPI CSI-2 RX to VDMA

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Hello,

I have a camera routed to a MIPI CSI-2 RX block, which in turn is routed to a VDMA and then the processor. I'm using a ZynqMP UltraScale chip. When I initialize the camera I see the packet count registers in the MIPI D-PHY core of the MIPI CSI-2 RX block incrementing and then wrapping, but when I configure the VDMA from Linux and start capturing I don't see the S2MM IRQ Frame count increase to more than 2. I also don't see any data being sent between the MIPI CSI2 RX block and the VDMA using a ILA and trying to trigger on TVALID.

I've attached another ILA and read the following pins of the MIPI CSI-2 RX block:

  • video_resetn is 1
  • system_rst_out is 0
  • pll_lock_out is 1

I've attached a asciinema recording which continously prints select registers from the aforementioned IP as I try to run the VDMA. Play the recording using:

asciinema play 1556046907-camera-debug.asciinema.txt

I could use some help debugging why I don't see any frames being sent from the MIPI CSI-2 to the VDMA.

Best,

Philip

---

I also noticed there are either "!" or "?" marks on all the ports of the MIPI CSI-2 block. I'm not sure how to interpret those and couldn't find any information about them.

2019-04-23-170853_716x551_scrot.png
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Observer
Observer
1,159 Views
Registered: ‎06-28-2018

It turns out it was a issue with the cables.

View solution in original post

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Observer
Observer
1,367 Views
Registered: ‎06-28-2018

Also of note, one of our 4 MIPI CSI-2 data lane status registers is fixed at 0.

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Moderator
Moderator
1,289 Views
Registered: ‎10-04-2017

Hi @philipmolloy,

In your ILA is tready from the VDMA high?

 

-Sam

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Xilinx Video Design Hub
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Observer
Observer
1,262 Views
Registered: ‎06-28-2018

Thanks for taking the time to reply @Anonymous. TREADY is high.

2019-05-01-104239_1033x642_scrot.png
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Moderator
Moderator
1,244 Views
Registered: ‎10-04-2017

Hi @philipmolloy,

 

Can you attach your register reads?
This sounds like the core is not being initialized properly, have you gone over the general checks in Appendix B of PG232?

 

Thanks,

Sam

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Xilinx Video Design Hub
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Observer
Observer
1,230 Views
Registered: ‎06-28-2018

I've attached register dumps from Linux using devmem for each of the three components. I read the registers after initializing and starting the VDMA.

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Observer
Observer
1,229 Views
Registered: ‎06-28-2018
# ./debug.sh 

MIPI CSI-2 RX Controller Core Registers @ 0xa0000000

	Core Configuration	ENABLED 
	Interrupt Status	STOP  
	Clock Lane Information	STOP 
	Lane 0 Information	STOP 
	Lane 1 Information	STOP 
	Lane 2 Information	STOP 
	Lane 3 Information	STOP 

MIPI D-PHY Core Registers @ 0xa0010000

	Control			ENABLED 0x2
	Initialization timer	100000 ns
	Clock lane status	0x18
	Data Lane 0 Status	INITIALIZED STOP 
		Packet count:	51128
	Data Lane 1 Status	INITIALIZED STOP 
		Packet count:	0
	Data Lane 2 Status	INITIALIZED STOP 
		Packet count:	29468
	Data Lane 3 Status	INITIALIZED STOP 
		Packet count:	29468
	High-speed 0 settle	145 ns
	High-speed 1 settle	145 ns
	High-speed 2 settle	145 ns
	High-speed 4 settle	145 ns

AXI VDMA Register Space @ 0xa0020000

	S2MM Control		RUN CIRCULAR IRQFRAMECOUNT 
		IRQ Frame #:	0
		IRQ Delay #:	2
	S2MM Status		RUN 

		IRQ Frame #:	0
		IRQ Delay #:	2
	Vertical size		
		Lines of data:	1080
	Horizontal size		
		Size of data:	0
	Enable vert flip	ENABLE 
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Observer
Observer
1,214 Views
Registered: ‎06-28-2018

We were able to synthesize a new bitstream for the ZCU102 and capture data in Linux. One important distinction is that on our board  (as I referenced above) data lane 0 seems to be receiving twice the number of packets, while 1 does not receive any. The remaining lanes appear to behave normally.

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Observer
Observer
1,160 Views
Registered: ‎06-28-2018

It turns out it was a issue with the cables.

View solution in original post

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Moderator
Moderator
1,149 Views
Registered: ‎10-04-2017

Hi @philipmolloy,

 

Good job finding your issue.

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub