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Registered: ‎04-01-2008

HDMI 2.0 TX Native Video Timing question with 2 pixels per clock ..

I am attempting to use the HDMI 2.0 core in Native mode, and I need to convert a 1 pixel per clock timing interface, to a 2 pixel per clock interface for the HDMI 2.0 core.  I couldn't find any timing diagrams in any of the Xilinx Datasheets for the Native interface of the HDMI core, so I figured I would ask the community here if anyone has any experience with this kind of conversion. 


In my example project, I am using the HDMI 2.0 core (with the Video PHY) in Native mode.  The question I have is in regards to the DE (active video) timing and how long it is high and how it changes from 1 Pixel per clock to 2 pixels per clock.  

See the attached Diagram. 


My assumption is that the DE timing is devided by 2, and the FP timing takes up the slack? 


Thanks for the help. 

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Registered: ‎04-24-2014

You need to divide everything by 2 ... DE, HS, FP, BP, SYNC.

Basically, every video clock cycle, you are effectively sending two pixels.

Accordingly, the parameters mentioned above should be evenly divisible by 2.

It goes without saying that your video clock frequency will also go down by half.

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