HDMI 2.0 Tx and Rx Subsystems IP clocks

[doner_t]

Hello ,

I have seen two clocks coming from an external source into the HDMI Tx and Rx Subsystem IP example design in ZC706 board. I wonder that could I give the both HDMI clocks ( 148.5 MHz) from PS ( Zynq) side?

Best Regards,

[hpoetzl]

Hey @doner_t,

Typically something like 148.5MHz will not work out from the PS side because the PLL and dividers there are not capable to get the frequency exactly right, but you can get close with the FCLK and you can also use an MMCM/PLL on the PL side to generate the desired frequency from an FCLK.

Hope this helps,

Herbert

[doner_t]

Hello @hpoetzl, 

Thank you for reply. 

So I can use PS side clock (FCLK) with an Vivado Clock Wizard IP. So that I can produce the exactly 148.5 MHz or almost by this way. But I wonder that are HDMI data and clock signals synchronous to each other ? If they are synchronous, we may not use the an internal clock instead of external ones, right?  You understand me why do I try to use FPGA internal clock for HDMI implementation, because of my clock sources in custom board are limited. 

Best Regards,

[hpoetzl · Accepted solution]

Hey @doner_t,

Thank you for reply.

You're welcome!

So I can use PS side clock (FCLK) with an Vivado Clock Wizard IP.

Yes, that is possible.

So that I can produce the exactly 148.5 MHz or almost by this way.

Yes, for example 100Mhz FCLK and an MMCM with 37.125*4 will give you 148.5Mhz.

But I wonder that are HDMI data and clock signals synchronous to each other?

I'd suggest to use a SERDES for both, data and clock, but for HDMI, the phase relation does not really matter as long as the clock is common.

If they are synchronous, we may not use the an internal clock instead of external ones, right?

I have no idea what this means ...

You understand me why do I try to use FPGA internal clock for HDMI implementation, because of my clock sources in custom board are limited.

I understand that you want to use the FCLK instead of an external clock.

Best,

Herbert