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Adventurer
Adventurer
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Registered: ‎08-16-2017

HDMI/DVI RX on Zynq Ultrascale MPSOC

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Dear Experts,

We are investigating the use of the Xilinx MPSoC Ultrascaler to receive up to 3 HDMI sources. The IP core available seems to be the PG236 and this works well in the example design of the ZCU102. However, in our application limited to the use of ZU3EG, for this we see that video PHY IP cannot be used.

How can we receive HDMI on this device? If not, is there a workaround by adding 

How many HDMI video sources can be received? which device allows up to 3 channels?

Any help is most welcome

 

 

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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @ziladdev,

 

Were watari and florentw able to answer your question?

If anything was missed, please reply so that we can comment. If not, can you select one of their responses as the solution?

Thank you,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ziladdev 

 

What are your target resolution, framerate and pixel clock frequency ?

 

Best regards,

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Adventurer
Adventurer
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Registered: ‎08-16-2017

The maximum is 1080p 60Hz. But we are flexible on this, i.e. it could be lower.

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Teacher
Teacher
830 Views
Registered: ‎06-16-2013

Hi @ziladdev 

 

You can achive your target with TMDS, SelectIO, decoder and EDID (without Xilinx HDMI Rx IP).

 

https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

 

Also I suggest you to refer Digilent's DVI2RGB IP, too.

 

https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb

 

[Note]

I suggest you to consider lower pixel clock, if you are facing SI issue.

 

Best regards,

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ziladdev 

Just to add a bit on the really good answer from @watari (it deserve a kudos and to be marked as solution ;) ), Xilinx has an old xapp (xapp495) which is showing HDMI/DVI on TMDS interface. This is for Spartan-6 but could be adapted to Ultrascale+ as the code is fully available.

And another solution is potentially to have an external device managing the HDMI/DVI interface as the ADV7611. But you would need to add 3 of them on your PCB. You might want to refer to this blog which is using it.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎08-16-2017

Hold your horses....Ultrascale+ has no support for TMDS or am I mistaken here?

TMDS only availble on HR banks (according to UG571)...ZU+ has only HD and HP (Table 1-3 of ug1075). Please explain!

 

You gotta work harder to earn that Kudos :).

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ziladdev 

Yes you are right, I forgot about it while I already answered this in a previous topic:

https://forums.xilinx.com/t5/Versal-and-UltraScale/TMDS-on-ZU/m-p/916441/highlight/true#M8012

So as per this topic, you can use the xapp and then change the voltage level externally to complly with the HDMI spec.

Or you can use an external device as the ADV7611.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ziladdev 

 

Would you consider TMDS redriver and AC-coupled signal by receiving LVDS buffer on FPGA ?

 

Best regards,

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Adventurer
Adventurer
687 Views
Registered: ‎08-16-2017

That sounds as a magic solution. Which IO bank should we use and what IO standard ? as TMDS_33 is unavailble...

I will look more closely into the xapp and get back to you.

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ziladdev 

 

You can use both bank. Also, I already mentioned before about IO buffet type. 

 

Best regards,

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Highlighted
Moderator
Moderator
563 Views
Registered: ‎10-04-2017

Hi @ziladdev,

 

Were watari and florentw able to answer your question?

If anything was missed, please reply so that we can comment. If not, can you select one of their responses as the solution?

Thank you,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

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