01-07-2020 05:22 AM
We are investigating the use of the Xilinx MPSoC Ultrascaler to receive up to 3 HDMI sources. The IP core available seems to be the PG236 and this works well in the example design of the ZCU102. However, in our application limited to the use of ZU3EG, for this we see that video PHY IP cannot be used.
How can we receive HDMI on this device? If not, is there a workaround by adding
How many HDMI video sources can be received? which device allows up to 3 channels?
Any help is most welcome
02-04-2020 02:36 PM
01-07-2020 04:17 PM
You can achive your target with TMDS, SelectIO, decoder and EDID (without Xilinx HDMI Rx IP).
Also I suggest you to refer Digilent's DVI2RGB IP, too.
I suggest you to consider lower pixel clock, if you are facing SI issue.
01-08-2020 12:10 AM
Just to add a bit on the really good answer from @watari (it deserve a kudos and to be marked as solution ;) ), Xilinx has an old xapp (xapp495) which is showing HDMI/DVI on TMDS interface. This is for Spartan-6 but could be adapted to Ultrascale+ as the code is fully available.
And another solution is potentially to have an external device managing the HDMI/DVI interface as the ADV7611. But you would need to add 3 of them on your PCB. You might want to refer to this blog which is using it.
01-08-2020 07:11 AM
Hold your horses....Ultrascale+ has no support for TMDS or am I mistaken here?
TMDS only availble on HR banks (according to UG571)...ZU+ has only HD and HP (Table 1-3 of ug1075). Please explain!
You gotta work harder to earn that Kudos :).
01-08-2020 07:49 AM
Yes you are right, I forgot about it while I already answered this in a previous topic:
So as per this topic, you can use the xapp and then change the voltage level externally to complly with the HDMI spec.
Or you can use an external device as the ADV7611.
01-09-2020 05:59 AM
That sounds as a magic solution. Which IO bank should we use and what IO standard ? as TMDS_33 is unavailble...
I will look more closely into the xapp and get back to you.
02-04-2020 02:36 PM