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Observer
Observer
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Registered: ‎04-22-2018

HDMI Example design generation

Hi

  I am using the FPGA part xczu7ev-ffvf1517-1-i. I am trying to implement a HDMI receiver module and used the HDMI 1.4/2.0 Receiver Subsystem and generated it. When the synthesis of the IP is done I click on the OPEN IP EXAMPLE DESIGN.

Buy it throws a error window showing that the current example design runs only in the following eval boards.

How can I open the example design in the said part number.??

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Moderator
Moderator
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Registered: ‎04-09-2019

Hello @pragavish ,

The example design addressed in the PG236 , is for the evolution boards addressed in the Table 5-1. You can open the example design with the evolution boards, and can upgrade the design to the XCZU7EV-FFVF1517-1-i part number. While performing the upgrade of the design, user should take care of the reference clocks and the I/O Constraints as per their custom board selection.

With Regards,

Ashok

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Observer
Observer
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Registered: ‎04-22-2018

Hello @ashokkum 

Could you guide me as to how can I upgrade the eval board example design to my said part number. 

There seems to be many cores in that example design and I need info on how can I upgrade it.

Thank you so much

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @pragavish 

The blog article below is an example on how to move to another Xilinx board but this can be applied in your case as well:

Video Blog - How to port the HDMI example design for a VCU118 board to a VCU128 board in Vivado 2019.1

 

With that said, I would highly recommend you to start with the example design with the evaluation boards.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎04-22-2018

Hi @florentw @ashokkum 

Could you please guide me to Port the example design from eval board to the said FPGA part number.

Thank you

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Moderator
Moderator
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Registered: ‎04-09-2019

Hello @pragavish ,

Please go through the link which was shared earlier by @florentw . I hope it will be helpful to you. Kindly let me know, If you feel anything fishy about the procedure adressed in the above link. I will help You.

With Regards,

Ashok

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Observer
Observer
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Registered: ‎04-22-2018

Hello @ashokkum 

I generated a pass- through IPCORE using the XCZU104 Eval board. Once I generated the example design , I changed the part number to the said FPGA part number and upgraded the selected IPCORES.

Now an error is thrown in the "exedes_v_tpg_0_synth_1" file. I have attached the image of the log file.

Could you help me to avert the error

Thank you

IMG_20191129_170448__01.jpg
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Moderator
Moderator
465 Views
Registered: ‎11-09-2015

HI @pragavish 

You have 2 issues:

  • Your path is too long and will hit the 256 characters limit of the windows os
  • You have a space character in your project path

Please reduce the path of your project and remove any special/space character


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎04-09-2019

Hello @pragavish ,

Just adding one more note, along with the @florentw comments. Please take care of the path length. Because HLS IP's are sensitive to path length on windows platform. Since TPG is a HLS IP, You got the above error in the design.

With Regards,

Ashok

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Observer
Observer
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Registered: ‎04-22-2018

Hey @ashokkum @florentw 

   I changed the path of the file and the design got implemented. Thank you so much for your help

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Moderator
Moderator
316 Views
Registered: ‎04-09-2019

Hello @pragavish ,

I am Glad to hear this, and Thank You for updating the status.

With Regards,

Ashok

 

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