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Registered: ‎12-04-2019

HDMI FRAME BUFFER DESIGN 2020.1 VPHY FAILED

Hi,

A quick background on what I am trying to accomplish

I am trying to port DPU-TRD with HDMI FRAME BUFFER design in ZCU102 for designing hdmi application with DPU

I followed the following tutorials and instructions

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/767197238/HDMI+FrameBuffer+Example+Design+2020.1

I created a custom platform with this design for vitis accelerated application by following..

https://github.com/Xilinx/Vitis-In-Depth-Tutorial/tree/master/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104

After successfully integrating DPU with HDMI FRAME BUFFER Design (Screen shot below - Highlighted changes in the design -i.e adding clk and interrupt for DPU ) and generating linux image with vitis accelerated libraries,

 

Note: I modified xlconcat and inserted irq of axi_intc_0 to xlconcat[ in_0] which is connected to pl_ps_irq_0

hdmidpu.png

 

I get the following error in VPHY upon booting the image in ZCU102

The error is similar to

https://forums.xilinx.com/t5/Video-and-Audio/media-ctl-doesn-t-find-dev-media0-and-no-hdmi-rx-ss-gt-hdmi-info/td-p/1061528

But here the VPHY reports error.

 

 

 

 

 

[    6.805351] xilinx-vphy 80070000.vid_phy_controller: probe started
[    6.830078] xilinx-vphy 80070000.vid_phy_controller: VPhy version : 02.02 (0000)
[    6.837525] xilinx-vphy 80070000.vid_phy_controller: unable to request IRQ 2
[    6.844847] xilinx-vphy: probe of 80070000.vid_phy_controller failed with error -22
[    6.923597] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: xvphy/xgtphy not ready -EPROBE_DEFER
[    6.944569] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: xvphy/xgtphy not ready -EPROBE_DEFER
[   11.416508] xilinx-hdmi-rx 80000000.v_hdmi_rx_ss: xvphy/xgtphy not ready -EPROBE_DEFER
[   11.437800] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: xvphy/xgtphy not ready -EPROBE_DEFER

 

 

 

 

 

Also i get the following error

 

 

 

 

 

[    6.783535] dp159 0-005e: Identification registers do not indicate DP159 presence.

 

 

 

 

 

Note the errors

[ 6.837525] xilinx-vphy 80070000.vid_phy_controller: unable to request IRQ 2
[ 6.844847] xilinx-vphy: probe of 80070000.vid_phy_controller failed with error -22

here is the result of /proc/interrupts

 

 

 

 

 

root@zcu102_8b_2020_1:~# cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3       
  4:      38705      57570      47676      75838     GICv2  30 Level     arch_timer
  7:          0          0          0          0     GICv2  67 Level     zynqmp_ipi
  8:          0          0          0          0     GICv2 175 Level     arm-pmu
  9:          0          0          0          0     GICv2 176 Level     arm-pmu
 10:          0          0          0          0     GICv2 177 Level     arm-pmu
 11:          0          0          0          0     GICv2 178 Level     arm-pmu
 13:          0          0          0          0     GICv2 156 Level     zynqmp-dma
 14:          0          0          0          0     GICv2 157 Level     zynqmp-dma
 15:          0          0          0          0     GICv2 158 Level     zynqmp-dma
 16:          0          0          0          0     GICv2 159 Level     zynqmp-dma
 17:          0          0          0          0     GICv2 160 Level     zynqmp-dma
 18:          0          0          0          0     GICv2 161 Level     zynqmp-dma
 19:          0          0          0          0     GICv2 162 Level     zynqmp-dma
 20:          0          0          0          0     GICv2 163 Level     zynqmp-dma
 21:          0          0          0          0     GICv2 164 Level     Mali_GP_MMU, Mali_GP, Mali_PP0_MMU, Mali_PP0, Mali_PP1_MMU, Mali_PP1
 22:          0          0          0          0     GICv2 109 Level     zynqmp-dma
 23:          0          0          0          0     GICv2 110 Level     zynqmp-dma
 24:          0          0          0          0     GICv2 111 Level     zynqmp-dma
 25:          0          0          0          0     GICv2 112 Level     zynqmp-dma
 26:          0          0          0          0     GICv2 113 Level     zynqmp-dma
 27:          0          0          0          0     GICv2 114 Level     zynqmp-dma
 28:          0          0          0          0     GICv2 115 Level     zynqmp-dma
 29:          0          0          0          0     GICv2 116 Level     zynqmp-dma
 31:       1223          0          0          0     GICv2  95 Level     eth0, eth0
 33:        525          0          0          0     GICv2  49 Level     cdns-i2c
 34:        140          0          0          0     GICv2  50 Level     cdns-i2c
 35:          0          0          0          0     GICv2  42 Level     ff960000.memory-controller
 36:          0          0          0          0     GICv2  57 Level     axi-pmon, axi-pmon
 37:          0          0          0          0     GICv2 155 Level     axi-pmon, axi-pmon
 38:          0          0          0          0     GICv2 150 Level     nwl_pcie:misc
 43:         27          0          0          0     GICv2  47 Level     ff0f0000.spi
 44:          2          0          0          0     GICv2  58 Level     ffa60000.rtc
 45:          0          0          0          0     GICv2  59 Level     ffa60000.rtc
 47:       3619          0          0          0     GICv2  81 Level     mmc0
 48:        574          0          0          0     GICv2  53 Level     xuartps
 51:          0          0          0          0     GICv2  84 Edge      ff150000.watchdog
 52:          0          0          0          0     GICv2  88 Level     ams-irq
 87:          0          0          0          0     GICv2 126 Level     80040000.i2c
 88:          0          0          0          0     GICv2 125 Level     xilinx_framebuffer
 89:          0          0          0          0     GICv2 124 Level     xilinx_framebuffer
 95:          0          0          0          0  zynq-gpio  22 Edge      sw19
IPI0:      1334       2618       1803        989       Rescheduling interrupts
IPI1:        32        238        285        237       Function call interrupts
IPI2:         0          0          0          0       CPU stop interrupts
IPI3:         0          0          0          0       CPU stop (for crash dump) interrupts
IPI4:         0          0          0          0       Timer broadcast interrupts
IPI5:         0          0          0          0       IRQ work interrupts
IPI6:         0          0          0          0       CPU wake-up interrupts
Err:          0

 

 

 

 

 

Due to this VPHY error

/dev/media0 is not enumerated but /dev/video0 is enumerated

root@zcu102_8b_2020_1:~# media-ctl -d /dev/media0
Failed to enumerate /dev/media0 (-2)


root@zcu102_8b_2020_1:~# v4l2-ctl --all Driver Info: Driver name : xilinx-vipp Card type : vcap_hdmi output 0 Bus info : platform:vcap_hdmi:0 Driver version : 5.4.0 Capabilities : 0x84201000 Video Capture Multiplanar Streaming Extended Pix Format Device Capabilities Device Caps : 0x04201000 Video Capture Multiplanar Streaming Extended Pix Format Priority: 2 Video input : 0 Format Video Capture Multiplanar: Width/Height : 1920/0 Pixel Format : 'YUYV' Field : None Number of planes : 0 Flags : Colorspace : sRGB Transfer Function : Default YCbCr/HSV Encoding: Default Quantization : Default Selection: compose, Left 0, Top 0, Width 0, Height 0, Flags: Selection: compose_default, Left 0, Top 0, Width 1920, Height 0, Flags: Selection: compose_bounds, Left 0, Top 0, Width 1920, Height 0, Flags: Selection: crop, Left 0, Top 0, Width 0, Height 0, Flags: Selection: crop_default, Left 0, Top 0, Width 1920, Height 0, Flags: Selection: crop_bounds, Left 0, Top 0, Width 1920, Height 0, Flags: User Controls low_latency_controls 0x0098ca21 (int) : min=2 max=8 step=1 default=4 value=4

Also there are no flags like  hdmi_info, vphy_info in hdmirx and hdmitx sysfs

root@zcu102_8b_2020_1:~# ls /sys/devices/platform/amba_pl@0/80020000.v_hdmi_tx_ss
driver_override  modalias  of_node  power  subsystem  uevent

root@zcu102_8b_2020_1:~# ls /sys/devices/platform/amba_pl@0/80000000.v_hdmi_rx_ss/
driver_override  modalias  of_node  power  subsystem  uevent

How to resolve this issue?

Thanks in Advance

 

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2 Replies
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Registered: ‎12-04-2019

Would appreciate if anyone shed some info on how to fix this

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Registered: ‎12-04-2019

The design without accelerated components (i.e the base design as given in the xilinx wiki) is working and vphy reports no error.

My question is

can this design be modified as a vitis accelarated platform to deploy accelerated like DPU using vitis flow?

Also are there any example designs to display DPU's output (say bounding box) on to HDMI in PL? ( I could see VCU TRD ROI design implementing it but has it own plugins of gstreamer) Are there any examples that implement the same using low level libraries such as v4l2 and DRM?

looking forward for a reply

Thanks in advance 

 

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