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oupps
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Registered: ‎07-05-2018

HDMI IP on VCU118

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Hello.

 

We are working on a  Virtex ultrascale+ evaluation board (VCU-118) for HDMI. 

Following through the HDMI product guide(PG235), the HDMI IP is applicable for the VCU-118 with additional hardware, TB_FMCH-HDMI4K FMC card.

However, FMC HPC1 connections on VCU-118, shown in ug1124 document, and HPC FMC pin assignments on TB-FMCH-HDMI4K document do not seem to be compatible.

For example, the C2 pin on FMC HPC is assigned for TX_CH0_MGT_P in TB-FMCH-HDMI4K but C2 pin on FMC FPC in VCU-118 is assigned as N/A.

It does look like TB-FMCH-HDMI4K is not compatible with VCU-118, which seems to be different from the HDMI product guide.

In addition, we've followed the open IP example design in VCU-118 up to implementation, and the HDMI output ports are assigned to FMC+, not FMC which is for TB-FMCH-HDMI4K.

Therefore, our questions are "VCU-118 is compatible with TB-FMCH-HDMI4K ? If so, please advise us on how to connect both through FMC."

 

Thank you.

Sincerely,

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oupps
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Registered: ‎07-05-2018

@xud 

 

Sorry for the late update.

 

We successfully confirmed the color bar with VCU118 and the FMC card.

The problem, we thought, is the oscillator in the FMC card when we probed the signals from the oscillator.

Therefore, we changed the reference clock input from the pre-assigned internal oscillator to the FPGA outputs which are CLKIN_LVDS_P(LA00_CC_P), CLKIN_LVDS_N(LA00_CC_N). 

Of course, the corresponding register values for Si5324 in the FMC card were set up properly.

Thanks for your help.

 

Another question, for the next step, we want to try customizing the open IP example to our display pattern generator. 

To do so, simply, we want to eliminate a few blocks and modify IP options.

Although the modification in the block design is done, the Verilog code which is "exdes.v" is not allowed to change.

Is there a way to access the Verilog codes in the open IP example? (We've tried the IS_MANAGED and IS_LOCKED, but seems not to work.)

 

Sincerely

 

 

 

 

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florentw
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Registered: ‎11-09-2015

Hi @oupps 

Luckily, there is a Design and Debug Techniques blog article available for this:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Blog-How-to-port-the-HDMI-example-design-for-a-VCU118/ba-p/1027650

Therefore, my answer, Yes, the VCU-118 is compatible with the TB-FMCH-HDMI4K FMC card


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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oupps
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Registered: ‎07-05-2018

Hi @florentw 

 

Thanks for you reply.

 

I've noticed the FMC card can be inserted to FMCP connector as well as FMC, therefore, as you mentioned, I agree the VCU-118 is compatible with the TB-FMCH-HDMI4K FMC card.

With that hardware connection, I've followed the PG235 and got a result below.

Going through the result, I guess there is a problem with the GTREFCLK for TX configuration, but don't know why.

The I/O configurations of the FPGA and the TB-FMCH-HDMI4K FMC card match.

are there any options to solve this problem?

 

Thanks

tx_hdmi.PNG

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florentw
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Registered: ‎11-09-2015

HI @oupps 

Did you follow the blog article from my previous reply?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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oupps
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Registered: ‎07-05-2018

Hi @florentw 

 

Yes, we did. However, I think the blog article does not exactly match with our case because our evaluation board is VCU-118.

 

I believe that re-porting the open IP example for my case is not needed, am I wrong?

 

Thanks,

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florentw
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Registered: ‎11-09-2015

HI @oupps 

You are right sorry. I was mixing between VCU118 and VCU128.

Did you change the VADJ voltage to 1.8V on the VCU118? In the PG235 it is mentioned only for KCU105 but I think this should also be done for VCU118


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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oupps
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Registered: ‎07-05-2018

Hi @florentw 

 

As you guided, I will try to confirm the VADJ voltage.

 

However, I guess the VADJ voltage isn't the problem because all the DS-component LEDs in VCU118 are on.

(In PG235, the VADJ is powered when DS19 LED is ON)

 

If you have other considerations, please let me know.

 

Thanks

pg235.JPG

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@oupps 

Which Vivado version are you using? Can you ensure you keep cable plugged before you power up the board, and see if you can get good TX clock?

Can you take a picture on how you plug your FMC card to VCU118 board? Please also dump all the Video PHY register values, we will have better idea on what might wrong.

oupps
Visitor
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Registered: ‎07-05-2018

Hi, @xud 

 

Followings are replies to your questions

 

-Which Vivado version are you using?

  : I am using Vivado 2019. 2

-Can you ensure you keep cable plugged before you power up the board, and see if you can get good TX clock?

   : I plugged the HDMI cable before powering up the board. Now, I don't think to get a good TX clock because the LED assigned for clock locking signal (LED0 in the example) is off.

-Can you take a picture on how you plug your FMC card to VCU118 board?

   : Here is the picture

vcu118_rev.jpg

 

 

 

 

 

 

 

 

 

 

 

 

-Please also dump all the Video PHY register values, we will have better idea on what might wrong.

   : Could you tell me how to dump the Video PHY register values? Can I dump the register values through "dump/restore memory" in Vitis?

 

Thanks.

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@oupps 

Please attached your xci file, I will try to generate example design with same settings, and do some test on my end.

Regards,

Xu

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oupps
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Registered: ‎07-05-2018

Hi @xud 

 

I attached all the xci files in the open IP example.

 

If you need other information, please let me know.

 

Thanks

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oupps
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Registered: ‎07-05-2018

Hi, @florentw 

 

I confirmed the VADJ voltage is set to 1.8 V  in both the evaluation kit and the FMC card through FMC+. 

 

However, the result (No TX reference clock) is still same.

 

Thanks.

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@oupps 

I used your xci settings to generate VCU118 design, it was working fine at my end. Please use attached bitstream and elf to do some test at your end. Then we can know if the issue is related to your hardware or design.

Please also use "z" menu to print out interrupt log, then I will have more clue on what happens

4kp60.JPG

 

1080p60.JPG

 

oupps
Visitor
Visitor
540 Views
Registered: ‎07-05-2018

@xud 

 

Sorry for the late update.

 

We successfully confirmed the color bar with VCU118 and the FMC card.

The problem, we thought, is the oscillator in the FMC card when we probed the signals from the oscillator.

Therefore, we changed the reference clock input from the pre-assigned internal oscillator to the FPGA outputs which are CLKIN_LVDS_P(LA00_CC_P), CLKIN_LVDS_N(LA00_CC_N). 

Of course, the corresponding register values for Si5324 in the FMC card were set up properly.

Thanks for your help.

 

Another question, for the next step, we want to try customizing the open IP example to our display pattern generator. 

To do so, simply, we want to eliminate a few blocks and modify IP options.

Although the modification in the block design is done, the Verilog code which is "exdes.v" is not allowed to change.

Is there a way to access the Verilog codes in the open IP example? (We've tried the IS_MANAGED and IS_LOCKED, but seems not to work.)

 

Sincerely

 

 

 

 

View solution in original post

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@oupps 

Rather than modifing Verilog code, you need to open block design, and then deleted un-needed module from there.

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