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Visitor
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Registered: ‎02-13-2020

HDMI TMDS DATA formation

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Hi,

Am working on HDMI video project. I wanted to understand If we use Video PHY controller, then how it will convert TMDS data to AXI4 stream data. 

I have gone through the Video PHY user guide however I didn't find this information.Where I can find documents regarding this conversion?

Thank you!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: HDMI TMDS DATA formation

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@sudhanayaks 

Firstly you need to understand what's is Video PHY's job, and what is HDMI Subsystem IP's job in the whole system.

Video PHY is used to transmitter/Receiver TMDS data (through a level shifting which converts the voltage between TMDS level to the level accepted by GT), which contains 4 serial channels : 3 TMDS data channels and one TMDS clock channel. Then convert it to parallel data, which can be called link data or HDMI Stream. This data contains all the video, AUX, CTRL words and audio data.

HDMI Rx and Tx IP is used to decoder/encode the HDMI stream to Video stream, audio stream, etc.

Video Bridge (Video In to AXI4 Stream Out and AXI4 Stream to Video Out IP) is the subcore of HDMI Subsystem IP. They converts the video stream between native video domain to AXI4 Stream domain.

At receive side, HDMI Rx IP extract this HDMI stream, and then split it to native video, audio data stream. Then Video bridge (Video In to AXI4 Stream Out IP) converts it to AXI4 Stream Video data. It has been documented in PG236

"The HDMI 1.4/2.0 RX Subsystem is connected to a Xilinx Video PHY Controller, which takes electronic signals from an HDMI cable and translates it into HDMI stream. Then, the HDMI1.4/2.0 RX Subsystem converts the HDMI stream into video stream and audio stream. Based onthe configuration selected, the HDMI 1.4/2.0 RX Subsystem sends the video stream in eitherNative Video format or AXI4-Stream format together with the AXI4-Stream Audio to otherprocessing modules."

At transmit side, HDMI Tx IP is used to package Video data, audio data and associate AUX infoframe to HDMI stream (link data). Then Video PHY converts this parallel data to Serial data, then transmit it to HDMI TMDS cable through a level shifting. It also documented in PG235 :

"The subsystem converts the video stream and audio stream into an HDMI stream, based on the selected video format set by the processor core through the CPU interface. The subsystem thentransmits the HDMI stream to the PHY Layer (Video PHY Controller) which converts the datainto electronic signals which are then sent to an HDMI sink through an HDMI cable."

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Moderator
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Registered: ‎04-12-2017

Re: HDMI TMDS DATA formation

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Hello @sudhanayaks 

Video PHY IP doesn't convert TMDS data into AXI, its done by HDMI RX SS IP.

HDMI IP is called sub-sytem IP because it has native to AXI bridge. I will recommend you to refer following diagram for clarification from PG235 appendix A  page number 95.

https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_tx_ss/v3_1/pg235-v-hdmi-tx-ss.pdf

axitest.JPG

 

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Visitor
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Registered: ‎02-13-2020

Re: HDMI TMDS DATA formation

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Hi @kvasantr ,

Thank you for the quick response.

Video PHY converter will convert HDMI Video(TMDS) data into Link data ie  AXI4-Stream based tdata (PG230 Page no.16).

I just wanted to know how HDMI video(TMDS) data is formed using stream data. What kind of conversion IP is doing to get TMDS data.

Is there any document which explains about this?

Thank you!!

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Mentor
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Registered: ‎06-16-2013

Re: HDMI TMDS DATA formation

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2007

Re: HDMI TMDS DATA formation

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@sudhanayaksthe format of the data on the AXI-Stream based tdata is not documented because the Video PHY is not intended to be used as a stand alone IP.

This is can be found in paragraph 2 on page 6 of PG230, December 6, 2019.

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP is not intended to be used as a stand-alone IP and must be used with Xilinx Video MACs, such as the HDMI™ 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths. However, it is still important to understand the behavior, use, and any limitations of the transceivers. See the device specific transceiver user guide for details.

As @kvasantr mentioned the supported use case is to connect the Video PHY IP to the HDMI Subsystems.

If you want to work with the TMDS data, then you should do as @watari said and look at XAPP495.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Xilinx Employee
Xilinx Employee
285 Views
Registered: ‎08-02-2007

Re: HDMI TMDS DATA formation

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@sudhanayaks 

Firstly you need to understand what's is Video PHY's job, and what is HDMI Subsystem IP's job in the whole system.

Video PHY is used to transmitter/Receiver TMDS data (through a level shifting which converts the voltage between TMDS level to the level accepted by GT), which contains 4 serial channels : 3 TMDS data channels and one TMDS clock channel. Then convert it to parallel data, which can be called link data or HDMI Stream. This data contains all the video, AUX, CTRL words and audio data.

HDMI Rx and Tx IP is used to decoder/encode the HDMI stream to Video stream, audio stream, etc.

Video Bridge (Video In to AXI4 Stream Out and AXI4 Stream to Video Out IP) is the subcore of HDMI Subsystem IP. They converts the video stream between native video domain to AXI4 Stream domain.

At receive side, HDMI Rx IP extract this HDMI stream, and then split it to native video, audio data stream. Then Video bridge (Video In to AXI4 Stream Out IP) converts it to AXI4 Stream Video data. It has been documented in PG236

"The HDMI 1.4/2.0 RX Subsystem is connected to a Xilinx Video PHY Controller, which takes electronic signals from an HDMI cable and translates it into HDMI stream. Then, the HDMI1.4/2.0 RX Subsystem converts the HDMI stream into video stream and audio stream. Based onthe configuration selected, the HDMI 1.4/2.0 RX Subsystem sends the video stream in eitherNative Video format or AXI4-Stream format together with the AXI4-Stream Audio to otherprocessing modules."

At transmit side, HDMI Tx IP is used to package Video data, audio data and associate AUX infoframe to HDMI stream (link data). Then Video PHY converts this parallel data to Serial data, then transmit it to HDMI TMDS cable through a level shifting. It also documented in PG235 :

"The subsystem converts the video stream and audio stream into an HDMI stream, based on the selected video format set by the processor core through the CPU interface. The subsystem thentransmits the HDMI stream to the PHY Layer (Video PHY Controller) which converts the datainto electronic signals which are then sent to an HDMI sink through an HDMI cable."

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