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nikolamkg
Visitor
Visitor
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Registered: ‎05-18-2018

HDMI TX-only reference design timing problem

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Hello,

 

I have been trying to use HDMI TX-only design example in Vivado 2018.1 on ZCU102 evaluation kit. I create design from HDMI TX component, I only change from pass-through topology to TX-only, other parameters are left with their initial values, but after running synthesis I get timing violations for a lot of paths. I have attached .rpx and .txt timing reports. I have been stuck with this problem for several days now, and it seems no one reports the same problem.

 

Thanks for reply.

 

Regards

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nikolamkg
Visitor
Visitor
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Registered: ‎05-18-2018

@xud not sure why, but now everything seems to be working fine, and during implementation everything manages to be routed correctly, so there is no more timing problem. If I encounter the same problem ever again, I'll update you, but I have tried it several times in the last couple of days, and no more errors.

 

Regards

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watari
Professor
Professor
1,757 Views
Registered: ‎06-16-2013

Hi @nikolamkg

 

Your problem is hold timing violation.

Would you refer the following post ?

 

https://forums.xilinx.com/t5/Timing-Analysis/how-to-fix-hold-violation-any-general-solution/td-p/678977

 

Bst regards,

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florentw
Moderator
Moderator
1,693 Views
Registered: ‎11-09-2015

Hi @nikolamkg,

 

Are you building the example design directly from the IP? I.e. Add the IP in a design, select TX only in the IP gui and right click > open example design?

 

Is this flow failing? Could you share the xci file you are using?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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xud
Xilinx Employee
Xilinx Employee
1,658 Views
Registered: ‎08-02-2007

@nikolamkg can you attach the HDMI xci file please? I will try to reproduce the problem

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nikolamkg
Visitor
Visitor
1,977 Views
Registered: ‎05-18-2018

@xud not sure why, but now everything seems to be working fine, and during implementation everything manages to be routed correctly, so there is no more timing problem. If I encounter the same problem ever again, I'll update you, but I have tried it several times in the last couple of days, and no more errors.

 

Regards

View solution in original post

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florentw
Moderator
Moderator
1,627 Views
Registered: ‎11-09-2015

HI @nikolamkg,

 

As the issue is not happening anymore, could you kindly close the topic by marking your last reply as accepted solution to close the topic (click on the button "Accept as solution" below your reply).

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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