07-01-2020 08:17 AM
In our project we are going to use xc7k325tffg676-2. Our customer will design their own PCB so we can put IOB arbitrarily.
In design, we are going to use Xilinx's HDMI 1.4/2.0 Tx Subsystem IP together with Video PHY Controller.
I am looking at HDMI IP example design for KC705 board as a reference to our design. I noticed in GUI of Video PHY Controller, it does not use 4th GT Channel as TX TMDS Clock. If I put same parameters, that results that HDMI_TX_CLK_out can't be routed on GT pin locations. It is LVDS signal instead. We would rather use it as GT pin.
My question is, is there any electrical restriction that forbids me to put HDMI_TX_CLK_out in GT pin location? And if not, aside of using additional LUTs and FFs, are there any pros and cons by putting them together or separating them as in reference design?
07-06-2020 01:13 AM - edited 07-06-2020 01:15 AM
In the latest version of Video PHY, you can enable 4th GT channel as TMDS in IP GUI.
To support 4th GT channel, we need to use inrevium TB-FMCH-HDMI4K FMC daughter card, which has a mux to select between LVDS and 4th GT channel.
07-08-2020 05:35 AM
Thank you on your answer.
About that mux. As we don't have LVDS_clk and want to use as less hardware as possible on PCB, can that mux be put out? We are planning to connect 4th GT channel (clk) directly to the DP159. Can you please confirm us it will be electrically compatible that way?
07-08-2020 06:14 AM
I wanted to share the schematic in my last reply, it seems to be removed by the system.
If you want to save the LVDS IO from FPGA, yes, you can use GT 4th Channel.
What we have validated and confirmed it's working, is to use the mux TS3USB221RSER.
Probably there is another way to shift the GT data level to 3.3V DP159 clock, but it's beyond the scope of Xilinx support.
07-15-2020 03:57 AM
Hi @xud ,
I'm involved in the same project as @hrvoje.prgic , if you don't mind i would like to share in more detail what we need.
While the solution with clock mux TS3USB221RSER is a good backup, our customer will probably inquire why do we have top use a clock mux, while there may be cheaper/better alternatives for connecting the HDMI clock to DP159. Both chips (Xilinx FPGA and DP159) are part of the HDMI subsystem developed by Xilinx, so it seems logical to ask for a recommended solution. We assume that this issue was already solved, so we would like to avoid trial-and-error usually occurring when one changes a high-speed design.
If possible, please share a recommended solution (or multiple solutions, if there is no best practice). Thanks!
07-15-2020 05:35 AM - edited 07-15-2020 05:36 AM
DP159 is part of Xilinx board, but the onboard HDMI connector doesn't support 4th GT channel usage.
TS3USB221RSER is on inrevium TB-FMCH-HDMI4K FMC card, not part of Xilinx board. This is how we validate 4th GT channel as clock solution.
If you are looking for alternative solution, please work with your FAE, so he can discuss with Marketing about this.