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Registered: ‎09-14-2020

HDMI Tx IP Clocking Query

I am trying to get HDMI up and running on my ZCU102 ES2 board and I was reading the documentation for the HMDI tx 1.4/2.0 (pg235) and PHY(pg230) video controller IP. I loaded up the example design provided by Xilinx and I got quite confused by the Clocks provided. The Example design has a 100MHz and a 300Mhz clock (both from the Zynq processor). The different clocks available are s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, link_clk, and video_clk on the HDMI IP (page 53) and vid_phy_sb_aclk, vid_phy_axi4lite_aclk and drp clk on the PHY controller. Now all the clocks on PHY controller take the 100MHz source. The s_axis_video_aclk takes the 300MHz source.

Now this is what confused me. I recently got HDMI running on Zedboard and the clock I used for 1080p60Hz was 148.5MHz (which makes sense). Why does the example design not use this?

I am very confused as to what clock signals to use, whether  I should use the 148.5 or continue using what the example design does. Further the doc (pg235) talks about data, link, pixel and video clock which again got me confused.

Could someone explain what exactly these are and how I would go about deciding what to use?

Basically I need to interface this with a VDMA and display an Image stored in the DDR on a monitor (1080p60Hz).

Much Thanks!

(Ps - I am still going through the example codes on the SDK side. This really seems like handful!)

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Registered: ‎04-09-2019

Hello @SriramGangadhar ,

axis_video_aclk, axis_audio_aclk and axi_lite clock will configured by the clock wizards, which micro blaze (or) processor will generate these clocks based on the system requirement.

Also, video_clk and link_clks will take care by the video phy gt controller. this will generate these clocks based on the system requirement for the targeted resolutions. HDMI TX and HDMI RX clocks will get configure based on the line rate of the input video resolution. Also, the HDMI TX and RX clock frequencies can be read from the 0x020C and 0x0210 registers of video phy controller IP.

Hope this information is helpful to you.

Kind Regards,

Ashok.

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