cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rajatrao
Explorer
Explorer
1,379 Views
Registered: ‎08-04-2016

HDMI Tx error: DRM vblank wait timed out

Jump to solution

Hello,

I have a custom board (with a 7EV FPGA) largely based on ZCU106. The only difference in the HDMI Tx circuit is that we do not have a Si5319 clock generator; instead, we have Si5341. The GT refclk that the HDMI/VPHY Tx IP needs has a clock input of 148.5 MHz. In the device tree, this is declared as a "fixed clock" so that the DRM driver knows the frequency, but does not try to reprogram it. This clock entry is then put into the v_mix and hdmi_txss device tree nodes.

 

gt226_clk: gt226_clk {
			#clock-cells = <0>;
			clock-frequency = <148500000>;
			compatible = "fixed-clock";
		};

 

 

The other point of difference is that I'm only using DVI, not HDMI. However, in ZCU106, I've tried connected a DVI monitor to the HDMI port and the design works fine...so I'm guessing there's no issue there.

Now, when I boot (Petalinux again largely based on VCU TRD 2018.3), I get a long list of error messages from the HDMI IP and the DRM -

<Please check the boot.log attachment>

 

I believe this kind of error could happen when there's no clock input. But that's not the case here. The HDMI and VPHY logs indicate this -

 

root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# cat hdmi_info 

  Stream Info
 -------------
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000

  Stream Timing
 ----------------

        HSYNC Timing: hav=1920, hfp=88, hsw=44(hsp=1), hbp=148, htot=2200 
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=036, vtot=1125


Tx Info
--------
TX Mode - HDMI 
HDMI Video Mask is Disabled

Scrambled: 0
Sample rate: 1
Audio channels: 0

root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# cat hdmi_log  



HDMI TX log
------
Initializing HDMI TX core....
Initializing VTC core....
Reset HDMI TX Subsystem....
TX cable is connected....
TX Stream Start
TX Set Stream, with video mode (102)
TX Set Stream, with video mode (102)
root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# 
root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# 
root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# cat vphy_log



VPHY log
------
TX frequency event
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
root@zcu106_vcu_trd:/sys/bus/platform/devices/a0020000.v_hdmi_tx_ss# cat vphy_info 
TX: QPLL0
RX: CPLL
TX state: idle
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 20 - Clk1Div : 10 - Clk2Div : 20

Tx Ref Clk: 148500480 Hz

 

 

So, it looks like the VPHY has detected the 148.5 MHz clock and locked on to it. The error messages indicate that the HDMI VTC is disabled for some reason..? I would guess that the vblank interrupts are not occurring because of that. Any ideas what the problem might be? Does the DRM driver stack work with a fixed clock?

0 Kudos
1 Solution

Accepted Solutions
rajatrao
Explorer
Explorer
1,181 Views
Registered: ‎08-04-2016

I've been able to get both options working - GPIO toggle and register write to reset tx refclk status. I ended up adding the feature in the atomic_mode_set function of the hdmi drm driver.

 

yan-eng.ang@leica-microsystems.com,
I feel the 4th channel as clock would work in Linux as well if the device tree entry specifies this.

Also, for further debug, maybe you can check if the hdmi txss and the mixer are generating interrupts at the frame rate. If yes, then it's probably a physical problem. If not, then maybe it's a driver stack/HDL design problem.

View solution in original post

5 Replies
rajatrao
Explorer
Explorer
1,336 Views
Registered: ‎08-04-2016

I added a ton of debugging prints in the driver to track the flow and compare against the flow in ZCU106. Everything proceeds identically up to the point where ZCU106 executes the TxStreamUpCallback , but that never happens on our custom board. On ZCU106, the VTC is initialized as part of the TxStreamUpCallback, so that explains why our board fails.

Can anyone explain under what conditions the Tx Stream Up event occurs or why it wouldn't occur? I understand from the HDMI TX SS and VPHY user guides that this event indicates that the VPHY has locked-on to the clock and is ready to provide the clock to the HDMI TX SS. I see all the vphy_log messages as specified in the user guide. Yet, I do not see the Tx Stream Up event. Why is this happening?

I should probably point out another difference wrt ZCU106 - While the refclk_rdy input to the vphy on ZCU106 is from the clock generator, in our case, we've tied it in IPI. The polarity is set to "Active High" and the value is tied to 1.

0 Kudos
1,303 Views
Registered: ‎12-25-2018

Hi,

I am also having the same problem. Encounter [CRTC:32:crtc-0] vblank wait timed out on my custom Zynq Ultrascale+ board. I am using latest vivado 2020.1, Petalinux 2020.1 and Vitis 2020.1 to create linux image with HDMI Rx/Tx DRM image framework.

I am controlling VPHY refclk_rdy using GPIO. Not connected to the Clock synthesizer LOL. I know this will trigger Tx frequency event. When I use baremetal code on our custom board, is able to trigger the event. But using the DRM framework, it seems not working.

HDMI TX log
------
Initializing HDMI TX core....
Initializing VTC core....
Reset HDMI TX Subsystem....
TX cable is connected....
TX Stream Start
TX Audio Unmuted
TX Set Stream, with video mode (162)
TX Audio Unmuted
TX Audio Unmuted
TX Set Stream, with video mode (162)
TX Stream is Up

 

VPHY log
------
GT init start
GT init done
TX frequency event
TX timer event
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
RX frequency event
RX timer event
RX DRU disable
CPLL reconfig done
GT RX reconfig start
GT RX reconfig done
CPLL lock
RX reset done
RX frequency event
CPLL lost lock
RX frequency event
RX timer event
RX DRU disable
CPLL reconfig done
GT RX reconfig start
GT RX reconfig done
CPLL lock
RX reset done
RX MMCM reconfig done
RX MMCM lock
TX frequency event
CPLL lost lock
TX frequency event
RX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
TX MMCM lock
QPLL lock
TX reset done
TX alignment done
RX frequency event
RX timer event
RX DRU disable
CPLL reconfig done
GT RX reconfig start
GT RX reconfig done
CPLL lock
RX reset done
RX MMCM reconfig done
RX MMCM lock
root@petalinux_ccu:/#

 

Starting udev
[ 6.423449] udevd[169]: starting version 3.2.8
[ 6.428237] random: udevd: uninitialized urandom read (16 bytes read)
[ 6.434758] random: udevd: uninitialized urandom read (16 bytes read)
[ 6.441288] random: udevd: uninitialized urandom read (16 bytes read)
[ 6.452988] udevd[170]: starting eudev-3.2.8
[ 6.528537] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.528540] xilinx_vphy: loading out-of-tree module taints kernel.
[ 6.535790] xilinx-vphy 80040000.vid_phy_controller: probe started
[ 6.547625] xilinx-vphy 80040000.vid_phy_controller: VPhy version : 02.02 (0000)
[ 6.555163] xilinx-vphy 80040000.vid_phy_controller: probe successful
[ 6.567927] xilinx-hdmi-rx 80010000.v_hdmi_rx_ss: probe started
[ 6.574341] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probe started
[ 6.580265] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: hdmi tx audio disabled in DT
[ 6.591788] hdmirx_irq_handler(): HDMI RX SS is not initialized?!
[ 6.599919] xlnx-drm-hdmi 80020000.v_hdmi_tx_ss: probe successful
[ 6.602424] xilinx-hdmi-rx 80010000.v_hdmi_rx_ss: Direct firmware load for xilinx/xilinx-hdmi-rx-edid.bin failed with error -2
[ 6.606174] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 6.617455] xilinx-hdmi-rx 80010000.v_hdmi_rx_ss: Using Xilinx built-in EDID.
[ 6.624074] [drm] No driver support for vblank timestamp query.
[ 6.631279]
[ 6.631279] Successfully loaded edid.
[ 6.637153] xlnx-drm xlnx-drm.0: bound amba_pl@0:drm-dmaengine-drv (ops 0xffffffc010ca3cc8)
[ 6.642437] xilinx-video amba_pl@0:vcap_hdmi: Entity type for entity 80010000.v_hdmi_rx_ss was not initialized!
[ 6.650833] xlnx-drm xlnx-drm.0: bound 80020000.v_hdmi_tx_ss (ops xlnx_drm_hdmi_component_ops [xilinx_hdmi_tx])
[ 6.668521] xilinx-hdmi-rx 80010000.v_hdmi_rx_ss: probe successful


Encoders:
id crtc type possible crtcs possible clones
33 32 TMDS 0x00000001 0x00000000

Connectors:
id encoder status name size (mm) modes encoders
34 33 connected HDMI-A-1 1600x900 51 33
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
3840x2160 60.00 3840 4016 4104 4400 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: preferred, driver
4096x2160 60.00 4096 4184 4272 4400 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: driver
4096x2160 59.94 4096 4184 4272 4400 2160 2168 2178 2250 593407 flags: phsync, pvsync; type: driver
4096x2160 50.00 4096 5064 5152 5280 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: driver
4096x2160 30.00 4096 4184 4272 4400 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
4096x2160 29.97 4096 4184 4272 4400 2160 2168 2178 2250 296703 flags: phsync, pvsync; type: driver
4096x2160 25.00 4096 5064 5152 5280 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
4096x2160 24.00 4096 5116 5204 5500 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
4096x2160 23.98 4096 5116 5204 5500 2160 2168 2178 2250 296703 flags: phsync, pvsync; type: driver
3840x2160 60.00 3840 4016 4104 4400 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: driver
3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: phsync, pvsync; type: driver
3840x2160 50.00 3840 4896 4984 5280 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: driver
3840x2160 30.00 3840 4016 4104 4400 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
3840x2160 30.00 3840 4016 4104 4400 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
3840x2160 29.97 3840 4016 4104 4400 2160 2168 2178 2250 296703 flags: phsync, pvsync; type: driver
3840x2160 25.00 3840 4896 4984 5280 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
3840x2160 24.00 3840 5116 5204 5500 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
3840x2160 24.00 3840 5116 5204 5500 2160 2168 2178 2250 297000 flags: phsync, pvsync; type: driver
3840x2160 23.98 3840 5116 5204 5500 2160 2168 2178 2250 296703 flags: phsync, pvsync; type: driver
1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
1920x1080 59.94 1920 2008 2052 2200 1080 1084 1089 1125 148352 flags: phsync, pvsync; type: driver
1920x1080 50.00 1920 2448 2492 2640 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
1920x1080 30.00 1920 2008 2052 2200 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
1920x1080 29.97 1920 2008 2052 2200 1080 1084 1089 1125 74176 flags: phsync, pvsync; type: driver
1920x1080 25.00 1920 2448 2492 2640 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
1920x1080 24.00 1920 2558 2602 2750 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
1920x1080 23.98 1920 2558 2602 2750 1080 1084 1089 1125 74176 flags: phsync, pvsync; type: driver
1680x1050 59.88 1680 1728 1760 1840 1050 1053 1059 1080 119000 flags: phsync, nvsync; type: driver
1600x900 60.00 1600 1624 1704 1800 900 901 904 1000 108000 flags: phsync, pvsync; type: driver
1280x1024 60.02 1280 1328 1440 1688 1024 1025 1028 1066 108000 flags: phsync, pvsync; type: driver
1440x900 59.90 1440 1488 1520 1600 900 903 909 926 88750 flags: phsync, nvsync; type: driver
1920x1080i 30.00 1920 2008 2052 2200 540 1084 1094 1125 74250 flags: phsync, pvsync, interlace; type: driver
1920x1080i 29.97 1920 2008 2052 2200 540 1084 1094 1125 74176 flags: phsync, pvsync, interlace; type: driver
1920x1080i 25.00 1920 2448 2492 2640 540 1084 1094 1125 74250 flags: phsync, pvsync, interlace; type: driver
1280x800 59.91 1280 1328 1360 1440 800 803 809 823 71000 flags: phsync, nvsync; type: driver
1152x864 75.00 1152 1216 1344 1600 864 865 868 900 108000 flags: phsync, pvsync; type: driver
1280x720 60.00 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
1280x720 60.00 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
1280x720 59.94 1280 1390 1430 1650 720 725 730 750 74176 flags: phsync, pvsync; type: driver
1280x720 50.00 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync; type: driver
1024x768 60.00 1024 1048 1184 1344 768 771 777 806 65000 flags: nhsync, nvsync; type: driver
800x600 60.32 800 840 968 1056 600 601 605 628 40000 flags: phsync, pvsync; type: driver
720x576 50.00 720 732 796 864 576 581 586 625 27000 flags: nhsync, nvsync; type: driver
720x480 60.00 720 736 798 858 480 489 495 525 27027 flags: nhsync, nvsync; type: driver
720x480 59.94 720 736 798 858 480 489 495 525 27000 flags: nhsync, nvsync; type: driver
640x480 60.00 640 656 752 800 480 490 492 525 25200 flags: nhsync, nvsync; type: driver
640x480 59.94 640 656 752 800 480 490 492 525 25175 flags: nhsync, nvsync; type: driver
720x576i 50.00 720 732 795 864 288 580 586 625 27000 flags: nhsync, nvsync, interlace, dblclk; type: driver
720x480i 60.00 720 739 801 858 240 488 494 525 27028 flags: nhsync, nvsync, interlace, dblclk; type: driver
720x480i 59.94 720 739 801 858 240 488 494 525 27000 flags: nhsync, nvsync, interlace, dblclk; type: driver
props:
1 EDID:
flags: immutable blob
blobs:

value:
00ffffffffffff006198341278563412
0e1c010380a05a780aee91a3544c9926
0f5054210800714f81c0810081809500
a9c0b300010108e80030f2705a80b058
8a0040846300001e023a801871382d40
582c450040846300001e000000fd0018
4b0f8c3c000a202020202020000000fc
0058494c494e582048444d490a200185
02033bf15761101f041305142021225d
5e5f6065666263640716031223090707
6b030c001000783c2000200367d85dc4
01788007e30f01e0e200cf023a801871
382d40582c450020c23100001e08e800
30f2705a80b0588a0020c23100001e04
740030f2705a80b0588a002052310000
1e0000000000000000000000000000dc
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 0
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
6 non-desktop:
flags: immutable range
values: 0 1
value: 0
4 TILE:
flags: immutable blob
blobs:

value:
20 CRTC_ID:
flags: object
value: 32

CRTCs:
id fb pos size
32 36 (0,0) (3840x2160)
3840x2160 60.00 3840 4016 4104 4400 2160 2168 2178 2250 594000 flags: phsync, pvsync; type: preferred, driver
props:
22 ACTIVE:
flags: range
values: 0 1
value: 1
23 MODE_ID:
flags: blob
blobs:

value:
50100900000fb00f0810301100007008
78088208ca0800003c00000005000000
48000000333834307832313630000000
00000000000000000000000000000000
00000000
19 OUT_FENCE_PTR:
flags: range
values: 0 18446744073709551615
value: 0
24 VRR_ENABLED:
flags: range
values: 0 1
value: 0

Planes:
id crtc fb CRTC x,y x,y gamma size possible crtcs
31 32 36 0,0 0,0 0 0x00000001
formats: BG24 RG24
props:
8 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 1
17 FB_ID:
flags: object
value: 36
18 IN_FENCE_FD:
flags: signed range
values: -1 2147483647
value: -1
20 CRTC_ID:
flags: object
value: 32
13 CRTC_X:
flags: signed range
values: -2147483648 2147483647
value: 0
14 CRTC_Y:
flags: signed range
values: -2147483648 2147483647
value: 0
15 CRTC_W:
flags: range
values: 0 2147483647
value: 3840
16 CRTC_H:
flags: range
values: 0 2147483647
value: 2160
9 SRC_X:
flags: range
values: 0 4294967295
value: 0
10 SRC_Y:
flags: range
values: 0 4294967295
value: 0
11 SRC_W:
flags: range
values: 0 4294967295
value: 251658240
12 SRC_H:
flags: range
values: 0 4294967295
value: 141557760

Frame buffers:
id size pitch


root@petalinux_ccu:~# modetest -M xlnx -s 34@32:3840x2160-60@RG24
setting mode 3840x2160-60.00Hz@RG24 on connectors 34, crtc 32
[ 190.742959] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CRTC:32:crtc-0] flip_done timed out
[ 200.982947] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CONNECTOR:34:HDMI-A-1] flip_done timed out
[ 211.222941] [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [PLANE:31:plane-0] flip_done timed out
[ 211.334940] ------------[ cut here ]------------
[ 211.339554] [CRTC:32:crtc-0] vblank wait timed out
[ 211.344381] WARNING: CPU: 2 PID: 622 at drivers/gpu/drm/drm_atomic_helper.c:1467 drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290
[ 211.356447] Modules linked in: xilinx_hdmi_tx(O) xilinx_hdmi_rx(O) xilinx_vphy(O) uio_pdrv_genirq
[ 211.365314] CPU: 2 PID: 622 Comm: modetest Tainted: G W O 5.4.0-xilinx-v2020.1 #1
[ 211.373911] Hardware name: xlnx,zynqmp (DT)
[ 211.378080] pstate: 60000005 (nZCv daif -PAN -UAO)
[ 211.382855] pc : drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290
[ 211.389373] lr : drm_atomic_helper_wait_for_vblanks.part.0+0x274/0x290
[ 211.395889] sp : ffffffc014af3970
[ 211.399187] x29: ffffffc014af3970 x28: 0000000000000000
[ 211.404482] x27: 0000000000000005 x26: 0000000000000000
[ 211.409777] x25: ffffff8874dc7000 x24: 0000000000000001
[ 211.415072] x23: 0000000000000038 x22: 0000000000000001
[ 211.420366] x21: ffffff8874e91e80 x20: ffffff88766a6090
[ 211.425661] x19: 0000000000000000 x18: 0000000000000010
[ 211.430956] x17: 0000000000000000 x16: 0000000000000000
[ 211.436251] x15: ffffff887a063568 x14: ffffffffffffffff
[ 211.441545] x13: ffffffc094af36b7 x12: ffffffc014af36bf
[ 211.446840] x11: ffffffc01104c000 x10: 0000000000000000
[ 211.452135] x9 : ffffffc0110e1000 x8 : 000000000000029c
[ 211.457430] x7 : 0000000000000006 x6 : ffffffc0110e1095
[ 211.462725] x5 : 0000000000000003 x4 : 0000000000000000
[ 211.468019] x3 : 0000000000000000 x2 : 00000000ffffffff
[ 211.473314] x1 : 8a937dca3c194b00 x0 : 0000000000000000

root@petalinux_ccu:/# cat /sys/devices/platform/amba_pl@0/80020000.v_hdmi_tx_ss/hdmi_info

Stream Info
-------------
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 2
Mode: Progressive
Frame Rate: 60Hz
Resolution: 3840x2160@60Hz
Pixel Clock: 594000000

Stream Timing
----------------

HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400
VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250


Tx Info
--------
TX Mode - HDMI
HDMI Video Mask is Disabled

Scrambled: 1
Sample rate: 1
Audio channels: 0

root@petalinux_ccu:/# cat /sys/devices/platform/amba_pl@0/80020000.v_hdmi_tx_ss/hdmi_log

 

0 Kudos
rajatrao
Explorer
Explorer
1,280 Views
Registered: ‎08-04-2016

Hi yan-eng.ang@leica-microsystems.com ,

Thanks for pointing out that the refclk_rdy needs to be toggled. This is actually clearly described in Chapter 4 and 5 of VPHY PG, but I hadn't read it. I am considering two options here -

1. A GPIO that gets controlled from the driver which deasserts then asserts (after 10 ms) the refclk_rdy signal in the xlnx_drm_hdmi_encoder_enable function.

2. Write to bit 3 of the Clock Detector Control register (0x200), again in the xlnx_drm_hdmi_encoder_enable function.

I would expect both to work, but based on your logs, it looks like the GPIO solution needs extra care? I'll try out option 2 on my side. Let me know if you have any luck with option 1.

 

@florentw, @kvasantr : How about adding inherent driver support for option 2 based on 

(i) A device tree parameter that indicates that the clock is fixed, OR

(ii) In case the refclk_rdy is not connected to the clock generator's locked signal.

0 Kudos
1,257 Views
Registered: ‎12-25-2018

Hi rajatrao,

I have no experience in modifying the DRM framework to insert new functions. May need to study 1st how to modify it. I think one key difference is our VPHY configuration. I am using 4 GT for the Tx channel and enable 4th GT channel for TX TMDS clock. Need to find out from Xilinx is this configuration ok for DRM framework. The provided HDMI In/Out DRM example for VPHY is using difference configuration. Below is my settings.

 

drm_vphy_setting.jpg

 

0 Kudos
rajatrao
Explorer
Explorer
1,182 Views
Registered: ‎08-04-2016

I've been able to get both options working - GPIO toggle and register write to reset tx refclk status. I ended up adding the feature in the atomic_mode_set function of the hdmi drm driver.

 

yan-eng.ang@leica-microsystems.com,
I feel the 4th channel as clock would work in Linux as well if the device tree entry specifies this.

Also, for further debug, maybe you can check if the hdmi txss and the mixer are generating interrupts at the frame rate. If yes, then it's probably a physical problem. If not, then maybe it's a driver stack/HDL design problem.

View solution in original post