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Adventurer
Adventurer
747 Views
Registered: ‎06-25-2018

Hello,

In my design, the HDMI Tx is configured in AXI-Stream input mode.  The axis_aclk runs at 300MHz and the video clock comes from the board, for example 148,5MHz.

With this configuration, what should I expect the axis_tuser on the video-in AXI-Stream (the start of frame) to look like?  will the tuser pulses (qualified with tvalid and tready) be stable and equi-distant, meaning with the same number of axis_aclk between them?  I am relying on tuser to be stable and locked for another module.  Will that work?

Thanks,

Jacques

 

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Xilinx Employee
Xilinx Employee
700 Views
Registered: ‎08-02-2007

@jmcm

If you want to count the cycles between tuser, you need to check the valid cycle (both tvalid and tready are asserted). The valid cycles between 2 tuser pulse should be the same as active frame size/ppc.

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Xilinx Employee
Xilinx Employee
701 Views
Registered: ‎08-02-2007

@jmcm

If you want to count the cycles between tuser, you need to check the valid cycle (both tvalid and tready are asserted). The valid cycles between 2 tuser pulse should be the same as active frame size/ppc.

View solution in original post

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Adventurer
Adventurer
649 Views
Registered: ‎06-25-2018

Thanks.  This answers my question.

Jacques

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