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Adventurer
Adventurer
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Registered: ‎07-29-2013

HDMI doesn't work on a custom zynqmp board

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Hi, I have a custom ZYNQMP board with fixed GTX clock 148.5Mhz. So I don't need a Si5379 compared with ZCU106.

Use 4th GT Channel as TX TMDS Clock option also has been selected on my custom board. 

I commented the I2cClk and removed all funtion related to Si5324 from the HDMI Example on ZCU106 C project. Finally my custom board didn't work.

The info printf is:

----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
  HDMI TX version : 03.00 (0402)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000

        HSYNC Timing: hav=1920, hfp=88, hsw=44(hsp=1), hbp=148, htot=2200 
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=036, vtot=1125
Scrambled: 0
Sample rate: 0

Audio
---------
Format   : L-PCM
Channels : 0
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 0 Hz
TX: QPLL0
TX state: idle

QPLL0 settings
-------------
M : 0 - N : 0 - D : 0

TX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

I checked other registers, they are

hdmi phy 0x00c reg is 0 
hdmi phy 0x010 reg is C8000111 
hdmi phy 0x014 reg is 0 //not used in HDMI
hdmi phy 0x018 reg is 0 
hdmi phy 0x01C is 80808080
hdmi phy 0x020 reg is 4040404
hdmi phy 0x120 tx clock mmcm reg is 2
hdmi phy 0x138 reg is 0
hdmi phy Clock Detector (HDMI) 0x200 Control Register is 501 
hdmi phy Clock Detector (HDMI) 0x204 Status Register is B 
hdmi phy 0x208 Frequency Counter Timeout Register is 5F5E100

The function EnableColorBar() never runs. Who know why it happens.

Thanks for help.

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Highlighted
Adventurer
Adventurer
154 Views
Registered: ‎07-29-2013

The main reason is that the tx_refclk_rdy port has three requirements as the pg230 required.

image.png

 

 

 

 

 

 

I've set the tx_refclk_rdy satisfied the requirement, but the TX stream is down happens after I release the tx_refclk_rdy a few seconds.

reset tx_refclk_rdy
TX stream is up
--------
Colorbar :
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000
--------
TX stream is down

I printed the info of vphy log is :

VPHY log
------
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
TX frequency event
QPLL lost lock

I need to check it seriously.

View solution in original post

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Highlighted
Adventurer
Adventurer
155 Views
Registered: ‎07-29-2013

The main reason is that the tx_refclk_rdy port has three requirements as the pg230 required.

image.png

 

 

 

 

 

 

I've set the tx_refclk_rdy satisfied the requirement, but the TX stream is down happens after I release the tx_refclk_rdy a few seconds.

reset tx_refclk_rdy
TX stream is up
--------
Colorbar :
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz
        Pixel Clock:      148500000
--------
TX stream is down

I printed the info of vphy log is :

VPHY log
------
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
TX frequency event
QPLL lost lock

I need to check it seriously.

View solution in original post

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