03-12-2020 08:38 PM
03-12-2020 09:01 PM
03-12-2020 09:16 PM
03-13-2020 01:27 AM
Just build the design with 2018.x and then move it to 2019.2.
There is not much change between SDK and the embedded flow in Vitis. You should be able to find your way back with some work
03-15-2020 02:14 PM
So I took my best shot at moving everything over.
I don't know if this requires another thread, but when I'm trying to debug on the board I get an MMU section translation fault.
Any idea how to fix this?
03-16-2020 01:01 AM
Yes you should create a new topic as this is a different issue. The processor system design board is probably the best location for this.
I might be that the zynq is not properly configured in your vivado design or that the fsbl is not run before the application (make sure the check box is enabled in the run configuration) or something else.
You also might want to google this error message as somebody else might have already faced this issue