12-30-2017 11:18 PM
I am currently working on project based on video processing in which I have to use two video streams. I am new to video processing using FPGAs, so please excuse me if this is a bad question.
I use two Test Pattern Generator IPs(1080p, 60fps) to generate video inputs and I use two VDMAs for each stream to save the stream in DDR3 and retrieve data back. These two subsystems are working independently. I use two native FIFOs to control two video streams and allow both of video streams to access AXI bus and give me data to my FIFOs(Do I have to control it that way or does AXI bus handle it independently?). I connected tvalid signals and tready signals using programmable FIFO empty and programmable FIFO full signals appropriately. What my Intention is, once one fifo is almost full allow AXI bus to fill other FIFO while removing data from 1st FIFO. I want this kind of control mechanism to take both video inputs into my processing system.
However my problem is when I connect data given from one FIFO to my video out system(for the moment, bypassing my processing system) It gave me this kind of output as shown in video(monitor is on and off. Within on it is black display.). I connected tvalid and tready signals of video out ip appropriately using empty and full signals of FIFO. I managed to send tlast and tuser signals from VDMA ip to video output IP through same size of FIFO which is used for data. Read and write valid signals for that FIFO is same as the data FIFO. My expected output is solid red display in the monitor. I can't understand what is the wrong with my design. Can anyone guide me where do I have to check in my procedure?
12-31-2017 08:54 AM
I can't read what it says on the monitor
but bet its something like no input .
My recommendation would be to go to a simple design TPG to the output IP.
do you have a reference design that you could work with ?
Digital video either works or doesn't, so no input is an common start point,
12-31-2017 03:50 PM
It is difficult to understand your design without block diagram.
In this case, you should choose either video input to synchronize frame by V sync signal.
Here is my question and suggestion.
- How many frame do you use in VDMA ? I recommend to use one frame mode on each VDMA.
- Which do you choose either video input ? Confirm genlock mechanism on your design.
- How do you define video data's array ? (ex. define color format and depth as RGB 8bit by GUI) I just ask you.
- Recommend to upload your block diagram, if you want more detail answer.
03-05-2018 04:05 AM
Is everything clear for you? If you do not have more questions related to this, please kindly mark a response as solution to close the topic.
Thanks and Regards,