I am using system generator to do Hardware Co-Simulation of my projects . I have to add to my project the IP Divider Generator v3.0. So I start at first by testing the Ip core (Divider Generator v3.0) alone with hardware Co-Simulation and it works. After that, I added the ip core to my project but in Hardware Co-Simulation I get an error in the Synthesis process :
Loading core <dvider> for timing and area information for instance <Div>. INTERNAL_ERROR:Xst:cmain.c:3422:1.27 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
But when I work with ISE Project Navigator (without System generator ), I don't get this Synthesis error.