Hi, Thanks for the suggestion, I have solved it separetely, seems the error was I initialized the position of the FPGA in the device chain wrongly when I target new compilation target for hardware cosim.
I'm quite new in this topic, but I'd like to design some blocks using Xilinx System Generator together with Simulink and Hardware-co simulation online debugger. I found some ready-prepared config files for ML506 and ML402 (compact flash solution) to do it using ethernet co-simulation but I didn't find any configs for such a board like ML501. As far as I understand, You are using JTAG hardware cosim block for ML501, how to create it?, Did You find some tutors for this co-sim way?
The System Generator user guide explains how to add support for new JTAG co-sim boards. Take a look at the section titled "Supporting new platforms through JTAG Hardware Co-Simulation" uder "Using Hardware Co-Simulation".