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Observer
Observer
5,662 Views
Registered: ‎10-30-2007

Hardware Cosim one wrong output and one correct output

Hi all,
 
I have designed a DDC component with 2 outputs representing the I path and the Q path outputs. Simulation in Simulink works fine.
 
However when I did hardware cosim, the Q path hardware cosim output is fine but the I path hardware cosim output seem to have incur noise as that output seems to output a waveform that is off set by a magnitude of 2000 in the timescope domain. I would appreciate if some one has an answer to this. Thank You.
 
Regards.
 
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Xilinx Employee
Xilinx Employee
5,610 Views
Registered: ‎08-07-2007

I would suggest that you try generating this model with "create testbench" enabled and run the resulting HDL simulation both behavioral and post-PAR. 

For your co-simulation be sure you're running "single stepped" mode which will keep the hardware and software synchronized. 
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