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woodring
Adventurer
Adventurer
6,912 Views
Registered: ‎10-13-2007

Hardware In the Loop Cosim with DCM

Hi,

 Can anyone tell me the best way to use a DCM in a HWIL simulation. The proto card I'm using has a fixed 100MHz clock that I'd like to feed a DCM to get a 29.4MHz clock out of, but I'm not sure how to compile this in System Gen. for the HWIL target. Do I have to do an NGC netlist generation and add a DCM to the top level and if so how does that work with the HWIL sim?

 

Thanks,

CTW

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3 Replies
woodring
Adventurer
Adventurer
6,855 Views
Registered: ‎10-13-2007

Since no one has replied I'll post my latest observaitions.  It seems that for the HWIL simulation that the value used in the System Generator Simulink period controls the clock rate and the value of the fpga clock period doesn't come into play. I know my board runs at 100MHz and it is the only clock on it, but when I simulate and check the sample period of signals which have a sample period of 1, I see that the rate at which they are being sampled is 29.4MHz which is my System Gen period.   I think I may have seen somewhere in the docs that during single step HWIL simulation that SysGen controls the clock so apparently when the bit file is generated somehow my 100MHz clock is bypassed?

 What I'm not sure of now is if I bring my model into a bigger system that runs at the 100MHz clock rate, do I then have to add a DCM to get my 29.4MHz clock to drive the portion of the design which I have modeled in Simulink?

 

CTW

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rjduran
Xilinx Employee
Xilinx Employee
6,852 Views
Registered: ‎08-02-2007

If your end goal is to take your Sysgen design and put it into a larger ISE design using a DCM then there are a few ways to go about this.

1. Use clock enables (Default) 

2. Use the Clock Generator (DCM) option from the Sysgen token

3. Use the Expose Clock Ports Option from the Sysgen token

 

Look at the System-Level Modeling in System Generator section in the Sysgen users guide for 10.1 under Synchronous clocking , starting on pg 25. There are explanations for each of the three options and how to use them. All of them seem like they could be valid solutions to your design, it just depends on how you want the Sysgen design to plug into the overall design. 

RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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woodring
Adventurer
Adventurer
6,801 Views
Registered: ‎10-13-2007

Yes, I read some of the sections you mentioned when I upgraded to 10.1 last week, however initially I was using 9.2 which does not have the DCM support in the Sysgen token.

 

CTW

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