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manvarjay
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Registered: ‎03-26-2012

How to cope up with large time simulation in Simulink.

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Hello there,

                I am reading a matrix file through "from file" block and give it to Black Box as shown in the attachment.

 

I am getting proper output as I need but as the verilog code in Block Box is too long I have to provide Simulation stop time in many lakhs (cycles) which take days to simulate. I want to know whether we can run simulink part and black box part with different frequencies!! Because once the file is read I am only concern about the Black Box part.

 

Whether different simulation modes(Accelerator, External etc.) are useful to this? I have tried them also but they give errors.

 

-
Jay Manvar.
match_hw_co.png
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vlavruhin
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Registered: ‎12-08-2010

Hi, Jay.

 

HW-cosimulation has two options for clocking of simulated model in FPGA:

1) single-step clock (default),

2) free-running clock.

 

There is a detailed description of these modes in System Generator User Guide (at page 240 for version 13.4):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_user.pdf


I want to know that whether we can run many clk cycles of black box for one simulation time?

Yes, you can. And that's exactly a free-running clock mode.

Best Regards,
Vitaly.

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mganders
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Registered: ‎12-08-2007

Hi Jay,

 

If you are doing image processing there is no way around the long simulation times associated with processing pixels. The simulink accelerator feature does not work with SysGen. If you remove the sysgen "black block" from your simulation it will speed up things significantly. You really should be doing one or the other, meaing simulation of sysgen and then to sped things up simulation using HW co-sim (Hardware in the loop).

 

Regards,

Mike

manvarjay
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Registered: ‎03-26-2012

Hello Mike,

 

                Thanks for the reply. I think image processing is not the mater of concern, whatever process is there in your black box is going to be executed, think about some other application which needs millions of clk cycle. So it is not about Image Processing.

                 And the other thing, I have also tried removing simulation part and kept only HW Cosim part in that case it gives 2.5 to 3 times faster output than the simulation time which is also not sufficient!

                 Is there any scope for speed up the thing by changing sample rate or simulink system period (sys. gen. block).

-
Jay Manvar.
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mganders
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Registered: ‎12-08-2007

Your best bet would be to get rid of the unbuffer block and send the data in parallel to the HWIL block, and in the FPGA using an upconverter block to serialize if necessary. The problem with serializing data (for image processing in particular) is that Simulink runs cycle based regardless of how much data you are sending. Meaning it takes the same amount of simulation time to process a single bit/pixel as it does a 32b word. So if you unbuffer a 16b word it will take 16 sim clocks. If you instead make the 16bits parallel, the data it takes a single sim clock.

 

 

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manvarjay
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Registered: ‎03-26-2012

Hey Mike,

 

I don't think serializing will panic much here because my problem is at black box. The data I am sending is around 20-30 so I just need 20-30 clk cycle (or simulation time) for that but the code to process that data after receiving the data (after 20-30 cycles) is taking millions of clk cycle, and as the code in black box and the simulink are synchronized this takes a long time.

So my problem is the synchronization between simulation time and the black box. I want to know that whether we can run many clk cycles of black box for one simulation time?

-
Jay Manvar.
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vlavruhin
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Registered: ‎12-08-2010

Hi, Jay.

 

HW-cosimulation has two options for clocking of simulated model in FPGA:

1) single-step clock (default),

2) free-running clock.

 

There is a detailed description of these modes in System Generator User Guide (at page 240 for version 13.4):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_user.pdf


I want to know that whether we can run many clk cycles of black box for one simulation time?

Yes, you can. And that's exactly a free-running clock mode.

Best Regards,
Vitaly.

View solution in original post

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manvarjay
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Registered: ‎03-26-2012

Hi Vitaly,
Once again thanks for the reply, actually I was trying the same for last two days but the error was somewhere else. I realize it when I made changes in I/O of verilog file which didn't reflect in the Black Box I/O. But the config file was modified. So I restart the MATLAB and made new model and everything is fine for LCD Display.

 

Still thanks a lot for the document http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/sysgen_user.pdf, actually I had the sysgen user guide but it explain only a bit about the same. This user guide helps to build explicit synchronization mechanism, which is needed to receive initial features from file and then I can do free running. But still I am getting some problem. If I can not sort it out then I will let you know.

-
Jay Manvar.
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