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embedded
Advisor
Advisor
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Registered: ‎06-09-2011

How to create IP with a created interface Definition

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Hi,

I am going to create an AXI_through IP block to connect two Video blocks with some changes of handshaking signals - M_axis_tid to S_axis_tuser. I tried two methods: first I tried create and package new IP. I chose Create AXI4 Peripheral. However, AXIS port doesn't have s0_axis_tuser. Then I tried create interface Definition, selected from axis_rtl interface definition and saved two xml files in a directory. The question is that how I can create an IP from this xml file. I do need a block which has all the video signalings (axis_tid, axis_tuser,..). I took a look at UG1118 and UG994. I could not find the next step on creating IP after defining Interface Definition.

So, I would appreciate any help.

 

Thanks,
Hossein
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embedded
Advisor
Advisor
407 Views
Registered: ‎06-09-2011

Hi @florentw 

Thanks for the follow-up. I was wondering where we can use those created interfaces in below picture?

Interface_Definition.png

 

As I could not find any document regarding how and where to use this created interface I created this post. However, I could eventually learn where and how we use it. When we have our own custom IP with specific interface signals we can use our created interface to show the Vivado how - logical connection - it must connect these custom interfaces - which pin of master to slave - in a custom IP with custom interface signals.

Thanks,
Hossein

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florentw
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Moderator
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Registered: ‎11-09-2015

HI @embedded 

From what I understand you would like to have an IP automatically generated after creating an interface. Correct?

If this is the case, this is not possible. The IP which are created with the AXI4/AXI4-Lite are generated from templates. The templates are not adaptable if you create a new interface.

So you will need to create the HDL for your IP from scratch (and then you can package it as an IP)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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joancab
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Teacher
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Registered: ‎05-11-2015

 

In HLS it's easy to work with streams with side channel signals, you may want to have a look at it.

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florentw
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Registered: ‎11-09-2015

HI @embedded 

Any update on this?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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embedded
Advisor
Advisor
408 Views
Registered: ‎06-09-2011

Hi @florentw 

Thanks for the follow-up. I was wondering where we can use those created interfaces in below picture?

Interface_Definition.png

 

As I could not find any document regarding how and where to use this created interface I created this post. However, I could eventually learn where and how we use it. When we have our own custom IP with specific interface signals we can use our created interface to show the Vivado how - logical connection - it must connect these custom interfaces - which pin of master to slave - in a custom IP with custom interface signals.

Thanks,
Hossein

View solution in original post

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embedded
Advisor
Advisor
406 Views
Registered: ‎06-09-2011

Hi @joancab ,

Thanks for your comment. Could you please give me a hint in which HLS document I have to look for it?

 

Thanks,
Hossein
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joancab
Teacher
Teacher
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Registered: ‎05-11-2015

 

Besides the basic UG902, I used the definitions in ap_axi_sdata.h to work with Tlast in my case. These signals are just structure members in HLS that you can read/ write and give any specific meaning.

florentw
Moderator
Moderator
381 Views
Registered: ‎11-09-2015

HI @embedded 


I was wondering where we can use those created interfaces in below picture?

Interface_Definition.png

 

As I could not find any document regarding how and where to use this created interface I created this post. However, I could eventually learn where and how we use it. When we have our own custom IP with specific interface signals we can use our created interface to show the Vivado how - logical connection - it must connect these custom interfaces - which pin of master to slave - in a custom IP with custom interface signals.


Yes this is correct, the main use case would be in custom IPs


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**