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dr.elichan
Contributor
Contributor
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Registered: ‎01-27-2019

How to determine the minium clock frequency for M_AXI_GPO_ACLK in a HDMI PASSTHROUGH application?

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M_AXI_GPO_ACLK is connected with s_axi_lite_aclk of VDMA and S00, M00, M01....ACLK of AXI interconnect.

 

I guess that s_axi_lite_aclk is only used to read/write register of VDMA and will only be done after each global reset. If so, it should not be very sensitive to clock frequency.

How about AXI interconnect clock? How will this clock be related to pixel frequency?

Also, what should be the proper way to estimate the minimum clock frequency for M_AXI_GPO_ACLK in a HDMI PASSTHROUGH application?

 

 

 

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florentw
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Registered: ‎11-09-2015

HI @dr.elichan 

The clock of M_AXI_GP0 will be related to the pixel clock. But you need to check the datawidth of the interface to have the relationship. Because the AXI VDMA might read/write multiple pixels at each clock cycle.

So if you have a stream RGB 8-bit (i.e. 24-bit data transferred each pixel clock cycles) but the AXI-MM of the AXI VDMA is 512-bit, the clock needed for the M_AXI_GP0 might be >= pixel_clock / (512/24).

With that said this will be the minimum requirement. In the system there are multiple things to take in account:

  • HDMI has blanking period. Thus the AXI VDMA could use it to buffer some data
  • The memory might be busy with other part of the system so not available 100% of the time
  • There is hand-checking process on the AXI interface to consider

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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florentw
Moderator
Moderator
293 Views
Registered: ‎11-09-2015

HI @dr.elichan 

The clock of M_AXI_GP0 will be related to the pixel clock. But you need to check the datawidth of the interface to have the relationship. Because the AXI VDMA might read/write multiple pixels at each clock cycle.

So if you have a stream RGB 8-bit (i.e. 24-bit data transferred each pixel clock cycles) but the AXI-MM of the AXI VDMA is 512-bit, the clock needed for the M_AXI_GP0 might be >= pixel_clock / (512/24).

With that said this will be the minimum requirement. In the system there are multiple things to take in account:

  • HDMI has blanking period. Thus the AXI VDMA could use it to buffer some data
  • The memory might be busy with other part of the system so not available 100% of the time
  • There is hand-checking process on the AXI interface to consider

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post