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Observer
Observer
8,552 Views
Registered: ‎04-16-2015

How to generate a complete interlaced video from frame buffer?

Hello,

 

I need to generate an interlaced output from progressive contents stored by VDMA. For the moment my source running in 1080p and I am trying to generate 1080i

 

I already read this: http://forums.xilinx.com/t5/Embedded-Processor-System-Design/How-to-generate-interlaced-video-from-frame-buffer/m-p/550794#M13715 and this: http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/simple-way-to-interlace-video/m-p/567924#M4939

 

but when I try to generate my output with mm2s_vsize = s2mm_vsize/2 or 540 it repeats each vertical pixel 2 times. The result is incredibly bad quality. In fact it draws same thing for both frame fields. I think I have to keep mm2s_vsize=1080 to have a complete 1080 line interlaced frame. But this way it needs both fields data to be one after another. I don't know how it is possible to configure s2mm to put it's data in right order. Or how to configure mm2s to generate a complete interlaced video from my progressive source.

 

Thank you in advance,

 

Payam

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Xilinx Employee
Xilinx Employee
8,548 Views
Registered: ‎08-02-2011

Hi Payam,

 

The trick is to make your stride 2x as long as your hsize.

 

This'll probably help :)

www.xilinx.com
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Observer
Observer
8,460 Views
Registered: ‎04-16-2015

Thank you for your answer,

 

I configured my VDMA with 4 frame buffers. To be able to create my FiledID signal from “mm2s_frame_ptr_out” output coming from my MM2S section. I considered frame 1 & 3 as field 0 and frame 2 & 4 as field 1.

I configured my field 1 read frame pointers one line further. So my interlaced video signal is perfect and there is no problem with my interlaced video output.

To be sure I will not generate two consecutive odd or even fields I have to configure my MM2S as genlock master repeat disable.

The problem is when I configure it as Master and S2MM as slave, internal genlock doesn't work as expected. And S2MM don't want to update all 4 frames and loops only between 2 or 3 frames. I verified “GenlockSrc” , “GenlockEn” and tried all possible “FRMDELAY” values. It updates all frames only when I configure genlock disable.

 

Is there any thing else to verify? What “WrPntrNum” used for? Or what “Controlling entity” is?

 

I don't know what is the best approach to generate my field_id signal without having 4 frame buffers and MM2S as master?

 

I am using Vivado 2015.1 on linux with this frame buffer configurations:

 

S2MM STRIDE = 2000 (1080p50)

0x00000000 VDMA S2MM Frame Pointer 1

0x01000000 VDMA S2MM Frame Pointer 2

0x02000000 VDMA S2MM Frame Pointer 3

0x03000000 VDMA S2MM Frame Pointer 4

MM2S STRIDE = 4000 (1080i50)

0x00000000 VDMA MM2S Frame Pointer 1

0x01002000 VDMA MM2S Frame Pointer 2

0x02000000 VDMA MM2S Frame Pointer 3

0x03002000 VDMA MM2S Frame Pointer 4

 

Thank you in advance,

Payam

 

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Contributor
Contributor
4,414 Views
Registered: ‎09-01-2015

Did this ever get resolved?  I am having a similar issue.  I get the interlaced out but as the VDMA does it's thing the odd and even fields do swap order periodically.

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