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Observer
Observer
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Registered: ‎09-06-2018

How to judge whether S2MM VDMA transceiver is accurate

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hi, 

 

 first   VDMA reg34= 0x15810

  after WC  VDMA reg34= 0x15010

   next VDMA reg34= 0x15010

...........................

next VDMA reg34= 0x15010

  from register  all the time  bit14 err_irq=1 .

 I can not  WC.

 What exactly is the problem?

How to judge whether S2MM VDMA transceiver is accurate?

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2019-06-21_20-21-58.jpg
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Observer
Observer
435 Views
Registered: ‎09-06-2018
After loading the software driver is normal.It should be related to initialization and reset

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @flomingo 

Bt 14 is 1 because you have an error (bit 4 is 1). Probably the VDMA was stopped


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-06-2018

bit0 =0 

 It's still working.

I debug .VDMA can also transfer data to ddr3.

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Observer
Observer
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Registered: ‎09-06-2018
if WC
I write 15810 , REG34=15010.
I write 15000,REG 34=15000. all the time .

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Moderator
Moderator
736 Views
Registered: ‎11-09-2015

HI @flomingo 

Can you try to write 0xFFFFFFFF in the register?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-06-2018
hi,@florentw
if i write 0xffffffff,then reg34=0x15810.
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @flomingo 

So you still have bit 4 is 1. This is why you still have an interrupt. So you need to check the following

  • Make sure that HSIZE and VSIZE are not 0 by reading reg 0x50 and 0x54
  • Add an ILA on the AXI4-Stream interface and check if there is no backpressure
  • Add and ILA on the AXI4-MM interface and make sure there is no error coming from the memory interface.
  • Check if the memory you are trying to access can be used

 

Once again, I would recommend to start with my Video Series 24: Using the AXI VDMA in Triple Buffer Mode, this should give you a good reference of a working design

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-06-2018

微信图片_20190627101055.jpg

 

 

@florentw  ila debug . wlast/BVALID  have 2 pluse in next to no time .  I  doubt it .

  Please help me.  in addition ,WC should be bit clear 。why write FFFFFFFF. 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @flomingo 

The 2 tlast can be explained if you are at the end of a frame. So you just sending the last burst of data. So it not always wrong.

You have to write 0xFFFFFFFF because the bits are cleared on a 1. Check p79 of pg020


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-06-2018

hi, florentw 

    please help me check 2019062802.ila (see the att). I feel the Wlast epresents the result of a burst of data. I can't understand VDMA completely. VDMA have "Write Burst Size" ,"Stream Data Width","Line Buffer Depth". I check Start and end bytes in h-line, i feel  it is right.

   My design: 16bit data come into VDMA. 

I check the reg before initial VDMA , i find the reg34=0x14811. I cannot also clear.

May I have your contact information?

  thank you 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @flomingo 

What is the size of your image? DO you know if what you are looking at is the end of the picture?

There is nothing wrong with having a smaller burst if this is the end of a line or frame

Did you try to run my example from Video Series 24: Using the AXI VDMA in Triple Buffer Mode?

If not please do, this way you can have a working example as reference.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @flomingo 

Do you have any udpate on this? Did you make any progress?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer
Observer
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Registered: ‎09-06-2018
After loading the software driver is normal.It should be related to initialization and reset

View solution in original post

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