How to output different line rate with MIPI TX-DPHY

[bihuf]

I'm developing a DSI design with K7 device. To verify different DSI display, my design needs to support generating DSI stream with different line rate. But the TX-DPHY IP seems only support fixed line rate.

As far as I know, the MIPI DPHY IP cannot support dynamic line rate change, as mentioned in another topic of "MIPI D-PHY CSI-2 receiver change line rate".

What should I do? Is there any alternative solution for this requirement?

Best regards.

[karnanl · Accepted solution]

Hello @bihuf

1. Yes, your understanding is correct. Unfortunately Xilinx MIPI D-PHY does not support  dynamic line rate change.

2. If you are planning to use Xilinx DSI TX Subsystem , your use-case is not supported.

Thanks
Leo

Note : 

    We do have a customer who use MIPI D-PHY TX  with dynamic line rate change.

    They generated all MIPI D-PHY TX IP with Shared logic in Example Design, and design a custom shared logic.

    It is possible because they are using their own CSI-2 TX controller, and building a custom shared logic by themselves.

[bihuf]

Hi, Leo

    Thanks for your answer. Very helpful for my design.

     To customize the shared logic, I need to confirm the difference between two TX-DPHY IPs with different line rates is only different MMCM configuration. And the successful customer case is much persuadable.

Thanks,

wenyong