How to recovery when the TVALID is deasserted ('0') before TLAST is asserted ('1') ?

[watari]

Hi all

I'd like to design HDMI input to HDMI output with xilinx IP at ZedBoard (Avnet) and TB-FMCL-HDMI (Tokyo electron device.

My design is used Video In to AXI4-Stream IP, VDMA IP, two Video Timing Controller IPs and AXI4-Stream to Video Out IP without AXI4-lite.

Now I encounter the AXI4-Stream to Video Out core fail to lock issue.

# Confirmation an so on

- Already confirmed behavior and waveform of Video In to AXI4-Stream,  VDMA IP, two Video Timing Controller IPs and AXI4-Stream to Video Out IP

=> It works fine except AXI4-Stream to Video Out IP

- Already modified IP setting on AXI4-Stream to Video Out IP in accordance with AR #58410.

# Question

Q1) According to AR #58410, AXI4-Stream to Video Out IP should correctly work reset sequence.

However I can't find it. How do I treat with reset sequence ?

Q2) According to AR #61430, user must assert TLAST with the last pixel of the line.However, I'm sure that it is difficult to keep this constrain during transition period. Like before VTC is stable.How do I recovery it from this situation , if system has a deadlock ?

Thank you.

Best regards,

[florentw]

Hi @watari,

I have read your description. I am not sure if your issue is really related to what your pointing to.

Could we start by doing basic debut on the AXI4S to video out IP:

• Are you looking at the signals locked, overflow and underflow? Are they as expected (lock high and overflow and underflow low)?
• Are you looking at the status output? What value do you have?

Regards,

Florent

[watari]

Hi @florentw

Thank you for your reply.

> Are you looking at the signals locked, overflow and underflow? Are they as expected (lock high and overflow and underflow low)?

Yes. We expect the followings (a or b) after reset sequence.

a)

locked = H

overflow = L

underflow = L

b)

locked = H

overflow = L

underflow = H

> Are you looking at the status output? What value do you have?

Please refer the attached png file.

I captured related signals via ILA on ZedBoard.

[note]

Each sync polarity is below.

HSYNC => Active high

VSYNC => Active high

Thank you.

Best regards,

[florentw]

Hi @watari,

You shouldn't be in underflow when runninng. This might be why it is not working.

You might want to check the input of the AXI4S to video out IP and see if there is enough data coming.

Regards,

Florent

[watari]

Hi @florentw

Thank you for your reply.

I know I shouldn't be in underflow and the route cause (locked is still low).

BTW, I attached my rough design diagram.

I already confirmed behaviour of "Video in-AXI4Stream", "Video Timing Controller (Detecter)", "VDMA", "Video Timing Controller (Generator)" and "AXI4Stream-Video out" via ILA by waveform.

They were fine except "AXI4Stream-Video out".

Also, I alreay checked two related Xilinx's ARs.

Now I suspect "AXI4Stream-Video out" is deadlocked when the TVALID is deasserted ('0') before TLAST is asserted ('1') by some chance.

Therefore, I'd like to know how to recovery when the TVALID is deassered ('0') before TLAST is asserted ('1').

[Note]

1)

I already confirmed the design by "Validate Design" and the result is fine.

2)

It works fine when I remove "AXI4-Stream - Video out" and add some control logic for VDMA.

But I'd like to use Xilinx's IP as much as possible.

So I'd like to resolve this issue.

Thank you.

Best regards,

[florentw]

Hi @watari,

Could you have a look to xapp1285? It is close from what you have (HDMI in + HDMI out on ZC702 (close from Zedboard)).

The code you help you in the steps.

I cannot really give you more I never had real issues with the AXI4S to video out IP (except what is flagging by overflow/underflow and locked)

I will see if I can think about something else

Hope that helps,

Regards,

Florent

[watari]

Hi @florentw

Thank you for your reply.

I already confirmed xapp1285. It is smiler my design. But an usage of VTC is very different than xapp1285.

BTW, I'd like to confirm state signal in v_axi4s_vid_out_v_4_0_5_sync by waveform via ILA.

Because of "state signal" is related with locked signal.

Could you tell me how to connect this signal ?

Thank you.

Best regards,

[florentw]

Hi @watari,

Is v_axi4s_vid_out_v_4_0_5_sync and internal signals? Then if you want to see it you need to had the ILA on the synthesized design.

Regards,

Florent

[watari]

Hi @florentw

Thank you for your reply.

> Is v_axi4s_vid_out_v_4_0_5_sync and internal signals?

Yes. It exists in AXI4Stream - Video out IP.

But I don't know how to connect it by board design.

> Then if you want to see it you need to had the ILA on the synthesized design.

I already implemented ILA to analyze some IPs behavior.

BTW, I read RTL file (AXI4Stream - Video out IP).

According to IP, it needs at least to input correct vblank signal, which is positive polarity.

Thank you.

Best regards,

[florentw]

Hi @watari,

According to IP, it needs at least to input correct vblank signal, which is positive polarity

See this post on the forum. There was a very good analysis from @toshas.

The timing detector needs at least 3 incoming signals (av/hb/vb or av/hs/vs)

Regards,

Florent

[florentw]

Hi @watari,

Any updates on this?

Best Regards,

Florent

[watari]

Hi @florentw

Here is current summary.

But I'm going to analyze "AXI4S to Video out" now and I will reply it if I got any good news.

- How to recovery when the TVALID is deassered before TLAST is asserted.

Need to assert vid_io_out_reset or !aresetn to recover this phenomenon.

Thank you.

Best regards,

[watari]

Hi @florentw

I'm sure what is route cause about my issue.

- According to RTL file of "AXI4 S to Video out", VTC_VBLANK should toggle after video signal is stable otherwise AXI4S to Video out unable to work even if VSYNC toggled.

In my case, I only use Active Video/VSync/HSync and VTC detector as lock detector and I connect Video in-AXI4S to VTC generator.

In this case, I suspect AXI4S to Video out malfunction. Because of VBlank is always low.

I think that this behavior is strange. VSYNC is very important and at least VSYNC is reference signal for video frame, too.

BTW, I'd like to modify this RTL and implement modified RTL.

Can I do it ?

If yes, where is RTL file for synthesis and implement in project ?

[note]

It may need to modify RTL file "Video-in to AXI4S", too.

Description of sof signal and vert_blanking_intvl are little strange.

Thank you.

Best regard,

[florentw]

Hi @watari,

BTW, I'd like to modify this RTL and implement modified RTL.

Can I do it ? If yes, where is RTL file for synthesis and implement in project ?

You can if the RTL is not encrypted. I don't know if it is the case. If not encrypted it should be under the ip in vivado

In my case, I only use Active Video/VSync/HSync and VTC detector as lock detector and I connect Video in-AXI4S to VTC generator.

In this case, I suspect AXI4S to Video out malfunction. Because of VBlank is always low

Could you try with a VCT to input the signals and make sure you have the same behaviour?

Best Regards,

Florent

[toshas]

@watari

"In my case, I only use Active Video/VSync/HSync and VTC detector as lock detector and I connect Video in-AXI4S to VTC generator.

In this case, I suspect AXI4S to Video out malfunction. Because of VBlank is always low."

This case should work!

 
Connect av/hs/vs to axi-vid-in, hb/vb connect to gnd.

Connect axi-vid-in timing interface to VTC.

Set VTC settings: detect - av/hs/vs, generate - av/hs/vs/hb/vb.

Connect all 5 timing signals from VTC to axi-vid-out (this core requires all 5 signals to be exist).

Also check that input timing is right. I mean frame size is line size x line count. Some camera modules has additional 4-5 pixels per frame. In this case additional fix is required.

[watari]

Hi @toshas

Thank you for your suggestion.

I think so, too. And I can't understand why my design malfunctions.

But I will confirm my design again.

> Also check that input timing is right. I mean frame size is line size x line count. Some camera modules has additional 4-5 pixels per frame. In this case additional fix is required.

In my case, it is for digital video, not camera.

But my environment is a little different and I may have overlooked irregular video signal, like you mentioned...

How do I describe "additional fix" without hb and vb signals ?

Thank you,

Best regards

[toshas]

Hi!

I suggest you to check your design in simulation environment.
It's time consuming but lead to success much more quickly.

Hb/vb isn't a problem as I mentioned above VTC will do this work for you.

If video is "irregular" (frame != lines*line length) additional vtg_ce management is required.