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Adventurer
Adventurer
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Registered: ‎02-24-2019

How to set an independent clock between two VDMAs in a HDMI( in & out) passthrough configuration

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I need to slower the clock rate between two VDMAs by creating another PL Fabric Clock. I want to keep the hdmi input and output at 60Hz while allowing a slower clock between two VDMAs because I need to allocate more time to do some calculation.

However, most of the time, I got no hdmi output if I set the clock to be below 141MHz.

Any advices.

 

hdmi_in_out.png

 

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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @eewse,

 

On the input side:60Hz write = slave, 30Hz read = Master

This will cause your input 60Hz to skip(drop) frames to keep up with the 30Hz Master. **because these are evenly divisible, this should be fine.

On the output side: 60Hz read = master, 30Hz write = Slave

This will cause the 60Hz master to control the frame rate and it will skip or repeat frames to keep up with the master. This should work, but it has the possibility of repeating 1 frame 3 times instead of 2.

I think it would be better to do the opposite of what you have suggested in both cases.  **I think both methods should work because the rates are evenly divisible, but I prefer sending the known data(30) further into the system before doing any dropping/repeating. 

This also follows the example in the PG under General use cases. (Page 72 of pg020)

 

Alternatively, you can use the VPSS to do this as well, but you will need 2 full VPSS instantiations, which may be too many resources if you do not need any other of the VPSS features.

 

 

 

 

 

 



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Xilinx Video Design Hub

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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @eewse,

Your AXI Memory interface and stream interfaces need to have enough throughput to handle the 60 frames per second.

It is likely you are starving a resource somewhere.

What are your video stream parameters? Bits per component, resolution, color-space, pixels per clock?

You will need these to figure out the bandwidth required to run the VDMA interfaces without starving the downstream video pipe.

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Xilinx Video Design Hub
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Adventurer
Adventurer
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Registered: ‎02-24-2019

How to present starving? Can the same frame in VDMA be read multiple times in asynchronous mode?

My setup requires the input to be at 60MHz while the image processing is 30Hz.

 

 

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Scholar
Scholar
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Registered: ‎03-28-2016

You likely need to use the VDMAs to create frame buffers that can be used to handle the different clock domains that you want to use.  A typical use case would have two frame buffers.  One for the input and one for the display.  The video would be input and stored to the input frame buffer.  Video would be read from the input frame buffer and processesed by your IP.  The results would be stored to the dispaly frame buffer.  The display logic would read the frame from the display frame buffer and send it out for display.  This setup would require 4 VDMAs: 1 to write the input, 1 to read for the IP, 1 to write for the IP and 1 to read for the display.

You can use the Gen-Lock feature to synchronize the VDMAs.  If the processing is running at 30 Hz, it would likely need to be the Gen-Lock master and control the movement of the frames in the buffers.

Typically, VDMAs are only used to read a frame once and then move to the next frame.  It might be possible to set it up to read each buffer multiple times, but I have not used it in that way before.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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Adventurer
Adventurer
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Registered: ‎02-24-2019

Is it for you have suggested?

Step 1.

write(60Hz): hdmi in to vdma0 

 Fsync s2mm tuser

GenLock: Slave

Step 2.

read(30Hz) : vdma0 to ip-in

Fsync None

GenLock Master

Step 3.

write(30Hz): ip-out vdma1

 Fsync s2mm tuser

GenLock: Slave

Step 4.

read(30Hz or 60Hz): vdma1 to video out

Fsync None

GenLock Master

Also,  should I set the GenLockRepeat=0 for  step 1 while GenLockRepeat=1 for step 4?

 

 

 

 

 

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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @eewse,

 

On the input side:60Hz write = slave, 30Hz read = Master

This will cause your input 60Hz to skip(drop) frames to keep up with the 30Hz Master. **because these are evenly divisible, this should be fine.

On the output side: 60Hz read = master, 30Hz write = Slave

This will cause the 60Hz master to control the frame rate and it will skip or repeat frames to keep up with the master. This should work, but it has the possibility of repeating 1 frame 3 times instead of 2.

I think it would be better to do the opposite of what you have suggested in both cases.  **I think both methods should work because the rates are evenly divisible, but I prefer sending the known data(30) further into the system before doing any dropping/repeating. 

This also follows the example in the PG under General use cases. (Page 72 of pg020)

 

Alternatively, you can use the VPSS to do this as well, but you will need 2 full VPSS instantiations, which may be too many resources if you do not need any other of the VPSS features.

 

 

 

 

 

 



Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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Adventurer
Adventurer
534 Views
Registered: ‎02-24-2019

@samk,

Many thanks

 

Eli

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