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Contributor
Contributor
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Registered: ‎01-27-2019

How to use VDMA as a video buffer so that a slow IP could produce a stable video output?

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In principle, I could use dynamic genlock plus triple buffer to ensure that there will have a stable video output(irrespective whether it is smooth playing or not)

To do so, I have to lower the clock associated with this slow IP so that it could complete the processing on time and could update the VDMA in a very slow manner.  However,

According to the Product Guide for the core:

"In asynchronous mode, the frequency of s_axi_lite_aclk <= m_axi_mm2s_aclk or m_axi_s2mm_aclk."

 

Because of this, I have to slower the clock associated with s_axi_lite_aclk as well.  But when I slower this clock to meet the above requirement, the screen starts flashing. But why?

As I am now running out of idea on how to ensure there will be a stable video output whenever a slow IP is connected. Any suggestion?

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Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

The difference is that in case one you run at high frequency but play with the hanchecking signal while in case 2 you are running at low frequency


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

HI @dr.elichan 

How slow is the "slow" IP?

I do not understand why you cannot run at a faster frequency... and I do not think reducing s_axi_lite_aclk is the correct option. The typical frequency for it would be probably around 50MHz. So the recommendation would be more try to run the streams clock faster. If an IP is not able to cope with this frequency, then the IP should apply backpressure (tready  = 0) so it is not receiving data when it cannot treat it.

If what you are trying to do is do processing from the PS, then you should not try to lower the input frequency. But you should control the buffer pointer so you can keep working on a buffer and maybe drop frames on the input.

I believe you need to rethink your system and see the issue from a different angle.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎01-27-2019

the slow IP is given by my client to be used in a hdmi passthrough application. The video output of this slow IP is not at a constant rate.

As it is a video streaming scenario, what will be the effect if I insert a back pressure by sending tready=0?

Also, any example on how to insert back pressure?

hdmi in -->(dynamic genlock master)vmda 0(dynamic genlock slave)->slow IP->(dynamic genlock master) vdma 1(dynamic genlock slave)-> hmdi out

to be exact, where should the tready signal be connected?

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Moderator
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Registered: ‎11-09-2015

HI @dr.elichan 

The tready should be on the AXI4-Stream interface of the slow IP. This is how the IP will handle not beeing ready to process a new data.

Then the effect will just be that the VDMA0 will not send new data while the downstream IP is not ready.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎01-27-2019

will the connection below be enough to stop  the  VDMA0 from sending any data to the SLOW IP?

VDMA0(M_AXIS_MM2S_TVALID)  <--- (IN_TREADY)SLOW IP

 

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Registered: ‎11-09-2015

HI @dr.elichan 

Yes, if tready is low, no data is transmitted.  This is part of the basics of AXI:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-1-Introduction-to-AXI/ba-p/1053914 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎01-27-2019

@florentw,

many thanks for your reply.  I have a much more clearer picture on how to pursue the testing.

1. By the way, what is the different between

VDMA0(M_AXIS_MM2S_TVALID) <--- (IN_TREADY)SLOW IP

vs

VDMA0(M_AXIS_MM2S) <--- (IN)SLOW IP

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Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

The difference is that in case one you run at high frequency but play with the hanchecking signal while in case 2 you are running at low frequency


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @dr.elichan 

Is everything clear for you on this topic? If yes, could you kindly mark a reply as accepted solution to close the thread?

Thanks.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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