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Contributor
Contributor
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Registered: ‎08-28-2017

How to utilize the Fsync_in in VTC ?

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Hi folks,

            We are using VTC in generation mode and utilizing Fsync_in port for configuring Extern Fsync with VDMA. Here is there any register configuration for Fsync_in in VTC  registers ?. If in case register configuration for Fsync_in, how to configure the register ?. 

 

Please suggest us regarding this issue.

 

Thank's and Best Regard's

 Vinod Sajjan

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @vinod.sajjan,

 

From your last post, there is no information whether you have checked the error register of the VDMA or the output information from the AXI4 2 video (overflow, underflow and locked).

You need to check this, it can give you information to debug.

 

How Exactly drive Extern Fsync port(in VDMA) from external trigger(with respect to aclk)?

From PG202:

VDMA.PNG

 

If we have extern Fsync mode in VDMA means i need connect Fsync_in for VTC?

No it can also be connected to something else. However, the VTC will link it to the video timing signal so this could have an inpact with the AXI4 stream to video out.

Remember that you need to have the fsync when you finished to read the frame. It cannot come at any time.

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar
Scholar
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Registered: ‎02-27-2008

in pg016

 

"FRAME SYNCHRONIZATION INPUT
This is a one clock cycle pulse (active high) input. The video timing
generator will be synchronized to the input if used."

 

No register settings involved.  Not that "it is important that fsync_in and
det_fsync are never asserted simultaneously" also from pg016.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
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Registered: ‎08-28-2017

Hi @austin,

 

Thank you for your time and support.

 

We Want to stop the VDMA for external trigger signal, for this we have enabled external Fsync in VDMA and we are utilizing Fsync_in in VTC by connecting external trigger signal to Fsync_in of VTC. We are getting output from VDMA, But we are not getting any output from Video out.

 

If we don't use Fsync_in of VTC and Fsync of VDMA we are able to get proper output from Video out when VDMA is in Free running mode. So we guess we have some timing issue.But I am not sure. Can you Please help me to solve this issue.

 

 

 

Thanks and regards

Vinod 

 

design_fsync.png
Xilinx1.JPG
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @vinod.sajjan,

 

We are getting output from VDMA, But we are not getting any output from Video out

Could you check the output locked, overflow and underflow for the video out IP?

Could you also add an ILA after the VDMA to see what could be wrong?

Did you check inside the VDMA register to see if you had any error?

 

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎08-28-2017

Hi @florentw,

 

Thank you for your time and support.

 

Yes we checked the VDMA register settings are correct and we checked before video_ out means read VDMA data that is coming (Checked with ILA).

 

Here VDMA register setting same as Free running mode without Fsync.

 

is there any VDMA register configuration for extern Fsync mode?

 

How Exactly drive Extern Fsync port(in VDMA) from external trigger(with respect to aclk)?

 

** If we have extern Fsync mode in VDMA means i need connect Fsync_in for VTC?

 

if i using extern fsync mode in VDMA means what all the changes i need do in side of VTC, VDMA, VIDEO_out, Please suggest me.

 

In last post i was attached design screenshot, is there any changes i need to do regarding Fsync of VDMA and Fsync_In of VTC, Please suggest me.

 

Please suggest me Regarding this issue.

 

Thanks and Best Regards

Vinod Sajjan 

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @vinod.sajjan,

 

From your last post, there is no information whether you have checked the error register of the VDMA or the output information from the AXI4 2 video (overflow, underflow and locked).

You need to check this, it can give you information to debug.

 

How Exactly drive Extern Fsync port(in VDMA) from external trigger(with respect to aclk)?

From PG202:

VDMA.PNG

 

If we have extern Fsync mode in VDMA means i need connect Fsync_in for VTC?

No it can also be connected to something else. However, the VTC will link it to the video timing signal so this could have an inpact with the AXI4 stream to video out.

Remember that you need to have the fsync when you finished to read the frame. It cannot come at any time.

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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