01-02-2021 08:35 AM
For using CSI-2, LVDS_25 and HSUL_12_S_HR are necessary, i.e. at least free 2 banks seems to be necessary.
So, I'd like to create an original board for ZYNQ.
Can a board work, on which only FPGA and DDR are? I do not need HDMI, ether etc. And, I need a board of very narrow footprint.
How should I treat balls not used, left open? Is there any schematic for that? And, is there any project for original boards?
01-02-2021 11:03 AM
Balls for IO may be left open or for more ESD protection, can be connected to ground. You will need more than the FPGA and DDR. You will almost certainly need a JTAG connection. If you are using a Zynq, a UART port is handy. You need something to boot from and hold the FPGA configuration. Quad SPI flash may be the easiest to use. You will probably need at least four power rails. For the sake of debug, tack on a couple LEDs. You will need at least one oscillator for the PS clock. Look at some schematics for the Xilinx eval boards. They will have more than you need, but you can see how the parts you need are connected.
What tool do you plan to use for board layout? If you are using DDR3 or DDR4, you will probably end up with at least an 8 layer board, more likely 12 layers.
01-02-2021 04:36 PM
@2U3 The bare minimums for a Zynq are:
- The Zynq, obviously
- Power supplies for the various sections and all the I/O banks, as well as external hardware (eg. level shifters)
- Some way to configure it. That may be JTAG (but you'll have to reconfigure it each time), QSPI flash, an SD card, etc. Obviously for QSPI flash you need some way of programming the flash too.
Most Zynq projects (but not all) will also have:
- DDR3 (Zynq 7000) or DDR4 (Zynq UltraScale+) RAM. This is obviously needed if you're going to do a lot with the PS.
- A UART port for debug.
Rather than doing your own board from scratch, you might find it easier to use something like the Trenz TE0820. It's already about as small as you can possibly expect (it's only 17mm wider than the FPGA itself) and it's got all the RAM, flash, etc built-in. Banks 64, 65, and 66 are all available and their voltage can be set by the board that the TE0820 plugs into.
01-03-2021 07:11 AM
Thank you for your answer and suggestion, bruce_karaffa and u4223374.
Yes I know that power rails, oscillator and JTAG are necessary, other than FPGA and DDR.
In any case, I need an original board finally. So, to begin with, I would like to create prototype with minimum chips on, where PS not used.
Then, I am worrying about if 8 layers being necessary. Is it still necessary for only 1GB DDR? I will use a minimum numbers of balls. And, I will use balls of more outer and more inner.
01-03-2021 07:52 AM
If you use a 16-bit DDR interface which is possible with a 7-series Zynq but not an Ultrascale Zynq, you will only have two byte lanes. Typically, you need a signal layer for each byte lane. You will need a couple reference planes. Ground is best, but power planes can be used if there are no discontinuities near the controlled impedance traces. You don't have any choice which pins to use if you want to use the PS side DDR interface. You can use the MIG to make a PL side DDR interface, but if you plan to ever use the PS, you will probably need a PS DDR interface.
01-03-2021 01:36 PM
If not using the PS, I would then stick an Artix.
The number of layers is not only a function of the number of signals (data and address and command) to route, it has also to do with the thickness between layers:
1 - signals need a specific impedance (50-100 ohm) that is usually achieved with a thin space (4-10 mils) to the reference layer, otherwise track width and space become unpractical. A typical PCB (1.5 mm = 63 mils) has 15 mils between layers with 4 layers, 11 mils with 6 layers and so on, so 6 layers is pretty much the minimum (there are 0.8 mm thick PCBs as well)
2 - Typical DDR memory chips are 0.8 mm pitch BGAs. Many of the balls have to go to internal layers. Full vias cannot be used for the minimum drill (the spec is 1:10, so for 1.5 mm PCB minimum drill is 0.15 mm). Add the smallest via donut and clearances and it won't fit between the pads. DDR chips are routed with microvias, made by laser ablation. Microvias have a limited depth, so again you cannot have thick dielectrics (few layers).
In short, DDR chips are not for low cost PCBs. DDR4 even worse than DDR3. Unless you order them in the 100s or 1000s, then they are as cheap as Arduinos.
01-07-2021 08:15 PM
I become to see that as constraints are very tight, it would be hard to design gerber.
T: thickness of each layer
N: number of layers
A diameter of via is related from T and N