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alvaro27
Adventurer
Adventurer
3,667 Views
Registered: ‎09-26-2007

INOUT PORT SYSTEM GENERATOR

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Hello.

 

I have a hdl design with INOUT ports (BUFIO). I have decided to create the same design using SysGen blocks. The problem is that there are only  In  (GateIn ) and Out  (GateOut) ports in SysGen.  I know that  I could generate a hdl netlist and then instantiate the BUFIO but  I would like to generate the bitstream from SysGen with the BUFIO already instantiated.

 

 

Does anyone how to manage this problem?

 

 

Thanks in advance,

 

Alvaro

 

Thank you for all.

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alvaro27
Adventurer
Adventurer
3,973 Views
Registered: ‎09-26-2007

 

Hello Vitaly,

 

thank you very much. I will follow the recommendations given in the Answer Record.

 

 

Best Regards,

 

 

Alvaro

 

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vlavruhin
Explorer
Explorer
3,646 Views
Registered: ‎12-08-2010

Hello, Alvaro.

 

It seems that there is no way to elude use of HDL in this case.

 

Look at the following Answer Record:

http://www.xilinx.com/support/answers/15505.htm

 

Best Regards,
Vitaly.
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alvaro27
Adventurer
Adventurer
3,974 Views
Registered: ‎09-26-2007

 

Hello Vitaly,

 

thank you very much. I will follow the recommendations given in the Answer Record.

 

 

Best Regards,

 

 

Alvaro

 

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