02-28-2012 01:20 PM
I have a hdl design with INOUT ports (BUFIO). I have decided to create the same design using SysGen blocks. The problem is that there are only In (GateIn ) and Out (GateOut) ports in SysGen. I know that I could generate a hdl netlist and then instantiate the BUFIO but I would like to generate the bitstream from SysGen with the BUFIO already instantiated.
Does anyone how to manage this problem?
Thanks in advance,
Thank you for all.
02-29-2012 04:52 AM