cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mspalpsahan
Adventurer
Adventurer
601 Views
Registered: ‎10-13-2018

IOStandard Type: I/O port mipi_dsi_clk_lp_n is Single-Ended but has an IOStandard of DIFF_HSTL_I_18

Jump to solution

hi everybody

i use to mipi_dsi_tx_subsystem_0 ip and i want connect with external pin. there is critical warning at the external pin. can you help me about critical warning.

problem 1: [DRC IOSTDTYPE-1] IOStandard Type: I/O port mipi_dsi_clk_lp_n is Single-Ended but has an IOStandard of DIFF_HSTL_I_18 which can only support Differential

problem 2 : The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

XC7Z020-1CLG400I

 

thank you

this is XDC file

set_property -dict { PACKAGE_PIN J14 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_clk_hs_n_1]; #DACK_N
set_property -dict { PACKAGE_PIN K14 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_clk_hs_p_1]; #DACK_P
set_property -dict { PACKAGE_PIN J16 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_n_1[0]]; #DA0_N
set_property -dict { PACKAGE_PIN K16 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_p_1[0]]; #DA0_P
set_property -dict { PACKAGE_PIN M15 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_n_1[1]]; #DA1_N
set_property -dict { PACKAGE_PIN M14 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_p_1[1]]; #DA1_P
set_property -dict { PACKAGE_PIN L15 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_n_1[2]]; #DA2_N
set_property -dict { PACKAGE_PIN L14 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_p_1[2]]; #DA2_P
set_property -dict { PACKAGE_PIN N16 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_n_1[3]]; #DA3_N
set_property -dict { PACKAGE_PIN N15 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_hs_p_1[3]]; #DA3_P

set_property -dict { PACKAGE_PIN G15 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_clk_lp_n]; #DBCK_N
set_property -dict { PACKAGE_PIN H15 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_clk_lp_p]; #DBCK_P
set_property -dict { PACKAGE_PIN G20 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_n_1[0]]; #DB0_N
set_property -dict { PACKAGE_PIN G19 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_p_1[0]]; #DB0_P
set_property -dict { PACKAGE_PIN H20 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_n_1[1]]; #DB1_N
set_property -dict { PACKAGE_PIN J20 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_p_1[1]]; #DB1_P
set_property -dict { PACKAGE_PIN G18 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_n_1[2]]; #DB2_N
set_property -dict { PACKAGE_PIN G17 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_p_1[2]]; #DB2_P
set_property -dict { PACKAGE_PIN F20 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_n_1[3]]; #DB3_N
set_property -dict { PACKAGE_PIN F19 IOSTANDARD DIFF_HSTL_I_18} [get_ports mipi_dsi_data_lp_p_1[3]]; #DB3_P

0 Kudos
1 Solution

Accepted Solutions
watari
Professor
Professor
508 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

As you may know, you must implement two kind of IO buffer escept US+ device, if you use MIPI.

One is differential IO for HS. The other is LVCMOS12 for LP.

 

In this case, "mipi_dsi_clk_lp_n" is used for LP. So you must implement IO buffer as LVCMOS12.

However, because you describe it as DIFF_HSTL_I_18, you are facing this issue.

 

Make sure your device and describe proper IO constraints in xdc file.

 

Best regards,

 

View solution in original post

0 Kudos
12 Replies
bruce_karaffa
Scholar
Scholar
597 Views
Registered: ‎06-21-2017

How do you use mipi_dsi_clk_lp_n in your code?  Do you instantiate a differential buffer?

0 Kudos
mspalpsahan
Adventurer
Adventurer
559 Views
Registered: ‎10-13-2018

hi

i not use code for mipp_dsi_clk_lp_n. i did design as (mipi_dsi_tx_subsystem_0) IP Block

 

Alpaslan SahanCapture.PNG

best regards

 

0 Kudos
watari
Professor
Professor
509 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

As you may know, you must implement two kind of IO buffer escept US+ device, if you use MIPI.

One is differential IO for HS. The other is LVCMOS12 for LP.

 

In this case, "mipi_dsi_clk_lp_n" is used for LP. So you must implement IO buffer as LVCMOS12.

However, because you describe it as DIFF_HSTL_I_18, you are facing this issue.

 

Make sure your device and describe proper IO constraints in xdc file.

 

Best regards,

 

View solution in original post

0 Kudos
mspalpsahan
Adventurer
Adventurer
465 Views
Registered: ‎10-13-2018

hi

thank you very much  for interested. no critical warning

there was one critical warning message while opening this design. can you help me at this issue

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

best regardsCapture.PNG

0 Kudos
watari
Professor
Professor
451 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

Would you share detail timing report to investigate the route cause of WNS ?

 

Best regards,

0 Kudos
mspalpsahan
Adventurer
Adventurer
446 Views
Registered: ‎10-13-2018

hi Watari

 

thank you fir interested.

 

best regards

0 Kudos
watari
Professor
Professor
393 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

Would you share timing report as plain text file to prevent garbled ?

 

Best regards,

0 Kudos
mspalpsahan
Adventurer
Adventurer
363 Views
Registered: ‎10-13-2018

hi

i am sorry to late i don't find time report file. can you describe it to me?

thank you very much.

best regards

Alpaslan Sahan

0 Kudos
watari
Professor
Professor
341 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

Would you use "report_timing" command on tcl console to output timing report ?

Also, using redirect to change output device from standard out to file is easy way to create it as file.

 

If you want to know detail about report_timing command, refer the result to add following option on report_timing command or UG835 tcl command reference guide.

 

report_timing -help

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug835-vivado-tcl-commands.pdf#page=1455

 

Best regards,

0 Kudos
mspalpsahan
Adventurer
Adventurer
320 Views
Registered: ‎10-13-2018

thank you

 

timing report

 

------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
| Date : Wed May 26 04:00:50 2021
| Host : DELL-LPTOP running 64-bit major release (build 9200)
| Command : report_timing -nworst 5 -path_type full -input_pins
| Design : TFT_LCD_Driver_wrapper
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.12 2019-11-22
------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) : -0.142ns (required time - arrival time)
Source: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_fpga_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.726ns (logic 1.942ns (41.091%) route 2.784ns (58.909%))
Logic Levels: 5 (CARRY4=2 LUT4=2 LUT6=1)
Clock Path Skew: -0.128ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.628ns = ( 7.628 - 5.000 )
Source Clock Delay (SCD): 2.985ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.083ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.150ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
propagated clock network latency
2.985 2.985
SLICE_X54Y75 FDRE 0.000 2.985 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
SLICE_X54Y75 FDRE (Prop_fdre_C_Q) 0.518 3.503 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/Q
net (fo=16, routed) 0.943 4.446 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/next_scl_state1_inferred__1/i__carry[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/I3
SLICE_X52Y77 LUT4 (Prop_lut4_I3_O) 0.124 4.570 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/O
net (fo=1, routed) 0.000 4.570 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0_0[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/S[0]
SLICE_X52Y77 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 5.102 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/CO[3]
net (fo=1, routed) 0.000 5.102 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry_n_0
SLICE_X52Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CI
SLICE_X52Y78 CARRY4 (Prop_carry4_CI_CO[0])
0.271 5.373 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CO[0]
net (fo=3, routed) 0.540 5.913 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/FSM_onehot_scl_state_reg[2][0]
SLICE_X54Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/I1
SLICE_X54Y78 LUT6 (Prop_lut6_I1_O) 0.373 6.286 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/O
net (fo=11, routed) 0.549 6.835 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0_n_0
SLICE_X55Y76 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/I0
SLICE_X55Y76 LUT4 (Prop_lut4_I0_O) 0.124 6.959 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/O
net (fo=10, routed) 0.752 7.711 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1_n_0
SLICE_X53Y75 FDRE r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
------------------------------------------------------------------- -------------------

(clock clk_fpga_0 rise edge)
5.000 5.000 r
propagated clock network latency
2.628 7.628
clock pessimism 0.229 7.857
clock uncertainty -0.083 7.774
SLICE_X53Y75 FDRE (Setup_fdre_C_CE) -0.205 7.569 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]
-------------------------------------------------------------------
required time 7.569
arrival time -7.711
-------------------------------------------------------------------
slack -0.142

Slack (VIOLATED) : -0.142ns (required time - arrival time)
Source: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_fpga_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.726ns (logic 1.942ns (41.091%) route 2.784ns (58.909%))
Logic Levels: 5 (CARRY4=2 LUT4=2 LUT6=1)
Clock Path Skew: -0.128ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.628ns = ( 7.628 - 5.000 )
Source Clock Delay (SCD): 2.985ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.083ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.150ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
propagated clock network latency
2.985 2.985
SLICE_X54Y75 FDRE 0.000 2.985 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
SLICE_X54Y75 FDRE (Prop_fdre_C_Q) 0.518 3.503 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/Q
net (fo=16, routed) 0.943 4.446 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/next_scl_state1_inferred__1/i__carry[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/I3
SLICE_X52Y77 LUT4 (Prop_lut4_I3_O) 0.124 4.570 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/O
net (fo=1, routed) 0.000 4.570 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0_0[0]
SLICE_X52Y77 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/S[0]
SLICE_X52Y77 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 5.102 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/CO[3]
net (fo=1, routed) 0.000 5.102 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry_n_0
SLICE_X52Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CI
SLICE_X52Y78 CARRY4 (Prop_carry4_CI_CO[0])
0.271 5.373 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CO[0]
net (fo=3, routed) 0.540 5.913 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/FSM_onehot_scl_state_reg[2][0]
SLICE_X54Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/I1
SLICE_X54Y78 LUT6 (Prop_lut6_I1_O) 0.373 6.286 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/O
net (fo=11, routed) 0.549 6.835 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0_n_0
SLICE_X55Y76 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/I0
SLICE_X55Y76 LUT4 (Prop_lut4_I0_O) 0.124 6.959 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/O
net (fo=10, routed) 0.752 7.711 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1_n_0
SLICE_X53Y75 FDRE r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
------------------------------------------------------------------- -------------------

(clock clk_fpga_0 rise edge)
5.000 5.000 r
propagated clock network latency
2.628 7.628
clock pessimism 0.229 7.857
clock uncertainty -0.083 7.774
SLICE_X53Y75 FDRE (Setup_fdre_C_CE) -0.205 7.569 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]
-------------------------------------------------------------------
required time 7.569
arrival time -7.711
-------------------------------------------------------------------
slack -0.142

Slack (VIOLATED) : -0.142ns (required time - arrival time)
Source: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_fpga_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.726ns (logic 1.942ns (41.091%) route 2.784ns (58.909%))
Logic Levels: 5 (CARRY4=2 LUT4=2 LUT6=1)
Clock Path Skew: -0.128ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.628ns = ( 7.628 - 5.000 )
Source Clock Delay (SCD): 2.985ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.083ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.150ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
propagated clock network latency
2.985 2.985
SLICE_X54Y75 FDRE 0.000 2.985 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
SLICE_X54Y75 FDRE (Prop_fdre_C_Q) 0.518 3.503 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/Q
net (fo=16, routed) 0.943 4.446 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/next_scl_state1_inferred__1/i__carry[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/I3
SLICE_X52Y77 LUT4 (Prop_lut4_I3_O) 0.124 4.570 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/O
net (fo=1, routed) 0.000 4.570 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0_0[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/S[0]
SLICE_X52Y77 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 5.102 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/CO[3]
net (fo=1, routed) 0.000 5.102 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry_n_0
SLICE_X52Y78 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CI
SLICE_X52Y78 CARRY4 (Prop_carry4_CI_CO[0])
0.271 5.373 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CO[0]
net (fo=3, routed) 0.540 5.913 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/FSM_onehot_scl_state_reg[2][0]
SLICE_X54Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/I1
SLICE_X54Y78 LUT6 (Prop_lut6_I1_O) 0.373 6.286 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/O
net (fo=11, routed) 0.549 6.835 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0_n_0
SLICE_X55Y76 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/I0
SLICE_X55Y76 LUT4 (Prop_lut4_I0_O) 0.124 6.959 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/O
net (fo=10, routed) 0.752 7.711 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1_n_0
SLICE_X53Y75 FDRE r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
------------------------------------------------------------------- -------------------

(clock clk_fpga_0 rise edge)
5.000 5.000 r
propagated clock network latency
2.628 7.628
clock pessimism 0.229 7.857
clock uncertainty -0.083 7.774
SLICE_X53Y75 FDRE (Setup_fdre_C_CE) -0.205 7.569 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]
-------------------------------------------------------------------
required time 7.569
arrival time -7.711
-------------------------------------------------------------------
slack -0.142

Slack (VIOLATED) : -0.142ns (required time - arrival time)
Source: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_fpga_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.726ns (logic 1.942ns (41.091%) route 2.784ns (58.909%))
Logic Levels: 5 (CARRY4=2 LUT4=2 LUT6=1)
Clock Path Skew: -0.128ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.628ns = ( 7.628 - 5.000 )
Source Clock Delay (SCD): 2.985ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.083ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.150ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
propagated clock network latency
2.985 2.985
SLICE_X54Y75 FDRE 0.000 2.985 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
SLICE_X54Y75 FDRE (Prop_fdre_C_Q) 0.518 3.503 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/Q
net (fo=16, routed) 0.943 4.446 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/next_scl_state1_inferred__1/i__carry[0]
SLICE_X52Y77 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/I3
SLICE_X52Y77 LUT4 (Prop_lut4_I3_O) 0.124 4.570 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/O
net (fo=1, routed) 0.000 4.570 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0_0[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/S[0]
SLICE_X52Y77 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 5.102 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/CO[3]
net (fo=1, routed) 0.000 5.102 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry_n_0
SLICE_X52Y78 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CI
SLICE_X52Y78 CARRY4 (Prop_carry4_CI_CO[0])
0.271 5.373 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CO[0]
net (fo=3, routed) 0.540 5.913 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/FSM_onehot_scl_state_reg[2][0]
SLICE_X54Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/I1
SLICE_X54Y78 LUT6 (Prop_lut6_I1_O) 0.373 6.286 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/O
net (fo=11, routed) 0.549 6.835 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0_n_0
SLICE_X55Y76 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/I0
SLICE_X55Y76 LUT4 (Prop_lut4_I0_O) 0.124 6.959 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/O
net (fo=10, routed) 0.752 7.711 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1_n_0
SLICE_X53Y75 FDRE r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
------------------------------------------------------------------- -------------------

(clock clk_fpga_0 rise edge)
5.000 5.000 r
propagated clock network latency
2.628 7.628
clock pessimism 0.229 7.857
clock uncertainty -0.083 7.774
SLICE_X53Y75 FDRE (Setup_fdre_C_CE) -0.205 7.569 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]
-------------------------------------------------------------------
required time 7.569
arrival time -7.711
-------------------------------------------------------------------
slack -0.142

Slack (VIOLATED) : -0.142ns (required time - arrival time)
Source: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: clk_fpga_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (clk_fpga_0 rise@5.000ns - clk_fpga_0 rise@0.000ns)
Data Path Delay: 4.726ns (logic 1.942ns (41.091%) route 2.784ns (58.909%))
Logic Levels: 5 (CARRY4=2 LUT4=2 LUT6=1)
Clock Path Skew: -0.128ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.628ns = ( 7.628 - 5.000 )
Source Clock Delay (SCD): 2.985ns
Clock Pessimism Removal (CPR): 0.229ns
Clock Uncertainty: 0.083ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.150ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_fpga_0 rise edge)
0.000 0.000 r
propagated clock network latency
2.985 2.985
SLICE_X54Y75 FDRE 0.000 2.985 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/C
SLICE_X54Y75 FDRE (Prop_fdre_C_Q) 0.518 3.503 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[9]/Q
net (fo=16, routed) 0.943 4.446 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/next_scl_state1_inferred__1/i__carry[0]
SLICE_X52Y77 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/I3
SLICE_X52Y77 LUT4 (Prop_lut4_I3_O) 0.124 4.570 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/REG_INTERFACE_I/i__carry_i_8/O
net (fo=1, routed) 0.000 4.570 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0_0[0]
SLICE_X52Y77 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/S[0]
SLICE_X52Y77 CARRY4 (Prop_carry4_S[0]_CO[3])
0.532 5.102 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry/CO[3]
net (fo=1, routed) 0.000 5.102 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry_n_0
SLICE_X52Y78 f TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CI
SLICE_X52Y78 CARRY4 (Prop_carry4_CI_CO[0])
0.271 5.373 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/clk_cnt_en1_inferred__2/i__carry__0/CO[0]
net (fo=3, routed) 0.540 5.913 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/FSM_onehot_scl_state_reg[2][0]
SLICE_X54Y78 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/I1
SLICE_X54Y78 LUT6 (Prop_lut6_I1_O) 0.373 6.286 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0/O
net (fo=11, routed) 0.549 6.835 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_3__0_n_0
SLICE_X55Y76 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/I0
SLICE_X55Y76 LUT4 (Prop_lut4_I0_O) 0.124 6.959 r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1/O
net (fo=10, routed) 0.752 7.711 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int[0]_i_1__1_n_0
SLICE_X53Y75 FDRE r TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]/CE
------------------------------------------------------------------- -------------------

(clock clk_fpga_0 rise edge)
5.000 5.000 r
propagated clock network latency
2.628 7.628
clock pessimism 0.229 7.857
clock uncertainty -0.083 7.774
SLICE_X53Y75 FDRE (Setup_fdre_C_CE) -0.205 7.569 TFT_LCD_Driver_i/sn65_edp/U0/X_IIC/IIC_CONTROL_I/CLKCNT/q_int_reg[5]
-------------------------------------------------------------------
required time 7.569
arrival time -7.711
-------------------------------------------------------------------
slack -0.142

 


report_timing: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2792.328 ; gain = 7.395

0 Kudos
watari
Professor
Professor
280 Views
Registered: ‎06-16-2013

Hi @mspalpsahan 

 

It seems fanout issue.

Would you consider to duplicate flip flop to reduce fanout issue or change strategy for implementation ?

 

Best regards,

0 Kudos
mspalpsahan
Adventurer
Adventurer
245 Views
Registered: ‎10-13-2018

Hi

thank you i will try 

best regards

 

0 Kudos