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Visitor
Visitor
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Registered: ‎01-21-2008

Illegal period of the System Generator block generated by AccelDSP

I use AccelDSP to generate a digital down converter (DDC) which operates in 21.5 MHz.
The Generate RTL report shows that both the startup clock cycles and hardware
clock cycles per design function call are 6. Then I use this block in the simulink
and set the system period to be 1/21.5 MHz. Then an error message shows that
 
The DDC_In port has a normalized period of 1, but the normalized period should be a multiple of 6 times the Simulink System Period.
This block is configured to have a hardware oversampling rate of 6.
Error occurred during "Rate and Type Error Checking".
 
How do I set simulink system period and FPGA clock period to run this DDC block properly ?
 
Thanks
 
Hou-Shin
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Anonymous
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Hi Hou-Shin,
 
Can you please zip up your  design example (both AccelDSP and SysGen model) and send it directly to me?
 
 
Thanks,
-Douang
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