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Visitor
Visitor
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Registered: ‎12-27-2017

Implement four MIPI CSI-2 Rx IPs in one HP Bank

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Hi,

I wan't to implement four MIPI CSI-2 Rx subsystem in one HP bank (Bank 65 of XCZU3CG-SFVC784). According to the descriptions of document PG202, it is possible to realize that. 

I tried to implement two MIPI IP cores at first, everything is OK. The bit file can be generated successfully.

But when I use four MIPI IP cores at the same time, some ERRORS occurred, show as below:

 

[Place 30-693] Unroutable Placement! PLL / BITSLICE_CONTROL component pairs are not placed in a routable site pairs. The PLL and it is load BITSLICE_CONTROLs need to be placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/shared_pll0_clkoutphy_out] >

design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst (PLLE4_ADV.CLKOUTPHY) is provisionally placed by clockplacer on PLL_X0Y4
design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[0].bs_ctrl_inst (BITSLICE_CONTROL.PLL_CLK) is provisionally placed by clockplacer on BITSLICE_CONTROL_X0Y8

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.pll0_clkout0_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y59

Clock Rule: rule_pll_bufg
Status: PASS
Rule Description: A PLL driving a BUFG must be placed in the same clock region of the device as the
BUFG
design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst (PLLE4_ADV.CLKOUT0) is provisionally placed by clockplacer on PLL_X0Y4
and design_1_i/mipi_csi2_rx0/mipi_csi2_rx_subsyst_0/inst/phy/inst/inst/bd_d10d_phy_0_rx_support_i/slave_rx.bd_d10d_phy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.pll0_clkout0_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y59

 

Any help would be much appreciated.

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Xilinx Employee
Xilinx Employee
276 Views
Registered: ‎03-30-2016

Hello Bruce

I see that all of your MIPI CSI-2 RX cores are configurated as "Included shared logic in core", it is not implementable since every cores will use one PLL, but there are only two of them on each bank.
Please see PG232, Chapter3 :
MIPI_mast_slv.png

You need to configure one (or two) of your cores, as a master core
and the rest of the cores as slave core.


Regards
Leo

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Xilinx Employee
Xilinx Employee
394 Views
Registered: ‎03-30-2016

Hello @bruce_li 

Please share all of your MIPI CSI-2 RX IP XCI files. I can double-check for you.

Regards
Leo

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Visitor
Visitor
323 Views
Registered: ‎12-27-2017

Hello Leo

Please see attachment.

Thanks

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Xilinx Employee
Xilinx Employee
277 Views
Registered: ‎03-30-2016

Hello Bruce

I see that all of your MIPI CSI-2 RX cores are configurated as "Included shared logic in core", it is not implementable since every cores will use one PLL, but there are only two of them on each bank.
Please see PG232, Chapter3 :
MIPI_mast_slv.png

You need to configure one (or two) of your cores, as a master core
and the rest of the cores as slave core.


Regards
Leo

View solution in original post

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Visitor
Visitor
261 Views
Registered: ‎12-27-2017

Hi Leo

Your answer is very helpful. The problem is solved now.

Thank you very much!