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jchewpoc
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Registered: ‎04-16-2019

Implementing Bypass mode for deinterlacer

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Hello Xilinx Forums,

I am having issues enabling the bypass mode for the deinterlacer VPSS. For this particular capture interface, I want to support both interlaced and progressive video. With that said, the deinterlacer is working when capturing interlaced video, but for progressive, I want to enable the bypass mode (grabbed from PG231):

Enabling and Disabling Bypass Mode
Deinterlacer IP supports six modes/algorithms including the bypass mode. Every mode/
algorithm is designated a number in the algorithm register, that is 0x0038 offset. So, the
value 0x6 represents the Bypass mode for the Deinterlacer IP.
To enable the bypass mode, 0x6 has to be written to the algorithm register (0x0038). This
will pass the input of the IP to the output without any change in the data and enable the IP
to the function in bypass mode.
To disable the bypass mode, any value other than 0x6 has to be written into the algorithm
register (0x0038).

After resetting the IPcore, I do a register write using devmem and the VPSS is not passing through any video data. Any more information on how to enable the bypass mode or suggestions on what I am doing wrong?

Thank you.

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jchewpoc
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Adventurer
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Registered: ‎04-16-2019

Hello @florentw ,

I reviewed the baremetal driver and was not able to see where they set bypass. I was able to get bypass working using some devmem writes:

devmem offset + 30 w 0x02 # color format
devmem offset + 10 w 1280 # width
devmem offset + 18 w 720 # height (interlaced)
devmem offset + 38 w 0x6 # bypass
devmem offset + 00 w 0x80 # first enable auto-restart
devmem offset + 00 w 0x81 # now enable

 

 

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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

Hi @jchewpoc 

Make sure you are using 2020.1. I cannot remember when the bypass mode has been implemented but this is in the later versions.

Then please try with the baremetal example. Xilinx does not support direct configuration through the registers, only using the drivers, which for the deinterlacer are available only in baremetal


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jchewpoc
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Registered: ‎04-16-2019

Hello @florentw ,

I forgot to mention that I am developing on Vivado 2019.1. I reviewed PG231 on DocNav 2019.1 for the VPSS, and the bypass enable option is there. I believe it 2019.1 may still support bypass mode. Unfortunately, transitioning to 2020.1 is not an option at this time.

Could you point me to the baremetal example for the VPSS deinterlacer?

Thank you.

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florentw
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Registered: ‎11-09-2015

Hi @jchewpoc 

I checked and the bypass feature has been implemented in 2019.1

For the example design refer to PG231 chapter 5.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

HI @jchewpoc 

Do you have any update on this? Were you able to make it work?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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jchewpoc
Adventurer
Adventurer
264 Views
Registered: ‎04-16-2019

Hello @florentw ,

I reviewed the baremetal driver and was not able to see where they set bypass. I was able to get bypass working using some devmem writes:

devmem offset + 30 w 0x02 # color format
devmem offset + 10 w 1280 # width
devmem offset + 18 w 720 # height (interlaced)
devmem offset + 38 w 0x6 # bypass
devmem offset + 00 w 0x80 # first enable auto-restart
devmem offset + 00 w 0x81 # now enable

 

 

View solution in original post