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Visitor
Visitor
2,901 Views
Registered: ‎02-28-2011

Input rate vs Output rate for FIR Compiler v5.0 clarification

Hi everyone,

 

I was wondering if someone could clarify my situation for me. I have a multirate system that is using a system generator with Clock Enables and a Simulink system period at 1/288 seconds. Say I have a signal running at 96 Hz that is going into a FIR Compiler (single rate Maximum possible HW oversampling) and coming out the other end, with Gateway Outs (Translate to outputs not checked) at each side of the FIR filter attached to "To Workspace" Simulink blocks (with inferred sample rates). Now I can verify that the sample rate going in is correct, but coming out I am getting a rate fo 288 Hz. I know the block is running at the Simulink system clcok of 288 Hz, but I can't seem to get the output to stay at 96 Hz. I am not really sure why the rate would be increasing since Clock Enables should be handling my enables etc. I also tried to implement my own enables and nd with no luck. Any help is appreciated even if it involves telling me I am missing something simple. Thanks for the help in advance.

 

 

UPDATE:  I would just like to add that when I put a down sample by 2 in after the FIR filter and before the Gateway out and To Workspace blocks, the rate drops to 48 Hz (which is way more than by two given previously the output was showing 288Hz). This is verified by comparing the number of samples recorded and the time the simulation ran.

 

 

UPDATE #2: I am pretty sure that I just answered by own question...I didn't provide a register on the output side of the filter, but had one before the input. Anyone feel free to verfiy/confirm my thoughts please.

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Xilinx Employee
Xilinx Employee
2,867 Views
Registered: ‎08-01-2007

Yes.  The way Sysgen works, is that it passes the rate along, and adding the downsample at the input will progegate it to the FIR Compiler.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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