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Observer
Observer
523 Views
Registered: ‎03-13-2017

Inrevium + Display Port example issue with DRP access of VideoPhy

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Hello

I am trying to run the DisplayPort TX example design then the passthrought example design for ZCU102 board + Inrevium TB-FMCH-VFMC-DP.

I have been able to generate and run successfully the Display Port 1.4 RX example design.

When I try to run the DP 1.4 TX I get the following error :

MobaXterm_2019-09-06_16-54-29.png

I have been able to figure out that the XVhy_DrpRd first call return in the PHY_Two_byte_set function return a failure.

I don't know if I am doing something wrong and I don't really now where to look to debug this issue.

More information on the setup :

- ZCU102 is a 0432055-05 number (new DDR4 chips) ==> I have found the fix of launching an fsbl without psu_init at the power up of the board and then launching the app (still without psu_init)

- The Inrevium board is attached to HPC0_FMC

- I have set VADJ_FMV to 1.8V on boot with the Board_ui.exe

- A computer is connected to the DP RX port and a 4K monitor to the DP TX port of the inrivium.

 

Do you have any idea to debug this situation ?

 

Thank you in advance for your answer,

Best regards,

Karvonz

 

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Observer
Observer
458 Views
Registered: ‎03-13-2017

Hello @florentw 

I finally found the fix just before the week end and was going to put the answer this morning.

You were seeing right with my problem I was running the fsbl for the ZCU102 platform and not the DP platform just compiled.

It fixed the drp failed and the design run well then. It's a bit weird that I can run the DP RX with a wrong fsbl and not the DP TX :D

Thank you for your support

Best regards,

Karvonz

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Teacher
Teacher
480 Views
Registered: ‎06-16-2013

Hi @karvonz 

 

Have you ever been updated a firmware of MSP430 which is Megachip's device ?

If no, would you update it whose firmware with a timestamp before July 5 2017 first ?

 

If you'd like to know the detail, would you refer a document of XTP433 ?

 

> - A computer is connected to the DP RX port and a 4K monitor to the DP TX port of the inrivium.

 

BTW, I'd like to know more detail to find a route cause.

Would you tell me the followings ?

 

- Would you use same version of tools between petalinux (boot loader), Vivado, XSDK and example design, if they are different ?

- What resolution and color depth do you choose at a computer ?

- Do you share your model name of 4K monitor ?

- Can you read DPCD register values by ex. Xilinx tool ?

 

Best regards,

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Moderator
Moderator
465 Views
Registered: ‎11-09-2015

Hi @karvonz 

This is the first time I se an error "DRP access failed" with the DP1.4 example design.

You said that you run a fsbl. Can you confirm that you run the fsbl build for the hardware platform of the DP1.4 example design?

Can you get a register dump of the video phy after the failure?

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Observer
Observer
459 Views
Registered: ‎03-13-2017

Hello @florentw 

I finally found the fix just before the week end and was going to put the answer this morning.

You were seeing right with my problem I was running the fsbl for the ZCU102 platform and not the DP platform just compiled.

It fixed the drp failed and the design run well then. It's a bit weird that I can run the DP RX with a wrong fsbl and not the DP TX :D

Thank you for your support

Best regards,

Karvonz

View solution in original post

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Moderator
Moderator
445 Views
Registered: ‎11-09-2015

HI @karvonz 

My guess why the DP1.4 RX only example was working is because you have run the psu_init before running the fsbl without a power cycling of the board. Thus the clock was properly set.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
374 Views
Registered: ‎08-28-2017

@karvonz 

Hi,

I am trying to get the displauport 1.4 Rx subsystem to work. I have the example design loaded. But when i check the ILAs in the examplde design i see only 0's on TDATA. Meaning its just a black screen. Did you face anything similar?

 

Regards,

Ska

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