cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mrbietola
Scholar
Scholar
1,256 Views
Registered: ‎05-31-2012

Interfacing Display port and SDI problem

Jump to solution

Hi, i'm tryng to interface the live input/output from Zynq MPSoC with SDI.

The idea is 

RX SDI -> DP Live input -> DP Live output -> TX SDI 

To do this i exploded the SDI TX subsystem to extract the VTC and axis to vid out components, in this way i can send timing to the DP live input.

I see that live video input wants hsync and vsynch, and it outputs  hsync and vsync, but the SDI TX Bridge wants hblank and vblank.

How to overcome this?

Can i send hblank and vblank to the live input hoping that they will be replicated on the live output?

0 Kudos
1 Solution

Accepted Solutions
mrbietola
Scholar
Scholar
1,012 Views
Registered: ‎05-31-2012

i found the problem. 

I wasn't aware that the FSBL had to be regenerated after i enabled the display port in the Zynq Processing unit.

The FSBL has to configure the clock towards the display port.

Now i see the video on the display live out even if the crominance are wrong

View solution in original post

11 Replies
florentw
Moderator
Moderator
1,194 Views
Registered: ‎11-09-2015

Hi @mrbietola 

I am not sure sending the vblank instead of the vsync will work as the Displayport controller might not be able to detect the timing..

What is the reason why you want to use the Displayport Controller here? I guess this is for the overlay feature?

The only solution I see might be to use a Video Mixer in the PL.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
mrbietola
Scholar
Scholar
1,168 Views
Registered: ‎05-31-2012

hi @florentw as you said we want to add a QT graphics application to add overlay to our SDI video.

The DP live input-> live output can work without user intervention right?

So if i set the connections correctly to the DP i should see the SDI video (without graphics) on output right?

What do you mean with the video mixer in the PL? I was told that the graphics generated by the DP is managed by the DPDMA, i don't know how to take that to the PL.

My desired goal would be to have 2 independent graphics with the QT on 2 sdi outputs, i was told that this is really hard to do, so we backup with 1 graphics channel only and 1 sdi output

0 Kudos
florentw
Moderator
Moderator
1,163 Views
Registered: ‎11-09-2015

Hi @mrbietola 


@mrbietola wrote:

hi @florentw as you said we want to add a QT graphics application to add overlay to our SDI video.

The DP live input-> live output can work without user intervention right? 

So if i set the connections correctly to the DP i should see the SDI video (without graphics) on output right?

[Florent] - Not really. The live output is just a duplication of the displayport output. Thus with the current driver, you will see data on the live output only if you have data on the displayport controller. I know some customers have been able to use the live input without the DP link to be up but this is not supported by the current driver.

What do you mean with the video mixer in the PL? I was told that the graphics generated by the DP is managed by the DPDMA, i don't know how to take that to the PL.

[Florent] - I believe this is the same way you could bring data to the DPDMA without using the live input. You just access the memory using a Video Frame buffer. Refer to the latest TRDs, they should use the displayport to display data from the PL without using the live input

My desired goal would be to have 2 independent graphics with the QT on 2 sdi outputs, i was told that this is really hard to do, so we backup with 1 graphics channel only and 1 sdi output


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
mrbietola
Scholar
Scholar
1,139 Views
Registered: ‎05-31-2012

Even with the standalone driver?

Actually i tried the avbuf driver but when i try to write to any dp registers, the software hangs, like if it's disabled.

In the ps processing system i set VPLL to DP Video only and i enabled DP without lane selection

0 Kudos
florentw
Moderator
Moderator
1,132 Views
Registered: ‎11-09-2015

HI @mrbietola 

Yes I think even the standalone driver does not expect this. This might be why you gets the hang if you have no lane selection


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
mrbietola
Scholar
Scholar
1,029 Views
Registered: ‎05-31-2012

A collegue of mine made it to work without lane selection, so i think the problem is elsewhere.

0 Kudos
mrbietola
Scholar
Scholar
1,013 Views
Registered: ‎05-31-2012

i found the problem. 

I wasn't aware that the FSBL had to be regenerated after i enabled the display port in the Zynq Processing unit.

The FSBL has to configure the clock towards the display port.

Now i see the video on the display live out even if the crominance are wrong

View solution in original post

florentw
Moderator
Moderator
1,005 Views
Registered: ‎11-09-2015

HI @mrbietola 

Good to know that you have found the issue


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
mrbietola
Scholar
Scholar
974 Views
Registered: ‎05-31-2012

i dig a little more and i found that i am able to run the standalone project with display port not because of the FSBL, but because of the psu_init flag in the debug options.

If i select the FSBL flow instead, the software hangs when initializes the display port.

So it seems that the FSBL and the psu_init are doing something different.

I tried to rebuild a BOOT.bin with the FSBL and the kernel hangs without error, i think because the display port not being activated.

So i need to figure out what the differences are between FSBL and psu_init

Shouldn't these be the same?

0 Kudos
florentw
Moderator
Moderator
968 Views
Registered: ‎11-09-2015

Hi @mrbietola 

Just sent you an email. Could you send me the HDF file you are using? I want to have a look as well.

You might want to enable the DEBUG flag in the FSBL to get some info on where this is hanging

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
mrbietola
Scholar
Scholar
958 Views
Registered: ‎05-31-2012

Hi @florentw thanks for your interest.

I found that the problem was in the FSBL project, even if i updated the hardware it was referencing and clean/built again the project, the code of the psu_init.c was not updated (insted the psu_init.tcl inside the _ide->psinit directory was updated with new values).

This lead to an incompatible configuration of the VPLL and everything hanged.

This problem is also present in the fsbl generated inside the hardware platform project (the project with green icon). Even if i updated the hardware specification, cleaned and built all, the psu_init.c was not updated.

Maybe i miss an obvious way to update things in Vitis, but i have frequently this problem also in the old SDK and i ended deleting the hardware and all bsp and generate again everything.

0 Kudos