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Anonymous
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Interlaced Video: 576i; Issue with VideoInAXISout block's output

I am in the process of interfacing a PAL decoder (TVP5150) to PAL encoder (ADV7392) using 720 X 576 interlaced video. Ultimately, this design will contain my custom HSL IP Core. Initially, I am adding only the VideoIn to AXIS-Out IP Core block. Please note that PAL Encoder requires only HSYNC and VSYNC signals along with data. My design is shown below. I have also uploaded a copy of my design on Dropbox.

 

 

Block Design Screenshot.png

 

 

I have noticed that without VDMA, the output of VideoInAXISout block is completely blank. There are no sync nor data signals at its output pins.

I have also attached a video of how this design's output looks like.

 

Additionally, if this helps: the question posted on this link too is regarding the same project. However, I am going one block at a time and therefore connected only VideoIn-AXISOut block for now.

 

Kindly let mw know what I have to change. The video seems like there's a problem with sync signals. I use Vivado 2015.2.

 

Note:

I have seen this link. However, I am enabling interlaced video support on GUI. Is it sufficient?

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

Hello Meghan,

 

I'm a little confused with what's going on here. You first posted a video where it looks like video is getting through, just distorted (like the interlaced handling isn't working properly.

 

However, you then say:

I have noticed that without VDMA, the output of VideoInAXISout block is completely blank. There are no
sync nor data signals at its output pins.

 

So are you trying to use the VDMA or not at the end of the day? If so, we should just put it in and ignore the passthrough case without the VDMA.

www.xilinx.com
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Anonymous
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Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

I was looking forward to your response. Thank you.

 

I meant initially when I had tried without VDMA, I was not getting any sync / data signals, hence I added a VDMA. (It isn't required though, but even if present it won't be an issue).

 

Yes. the video I posted clearly shows that there's an issue with interlacing / sync / I am not able to remove that distortion. Could you please tell me what to do?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

Ahh, I see. Thanks for the clarification.

 

If it were me, I'd isolate the output side and get that working first. I'd do this by removing the Video In to AXIS core and replace it with a TPG. Make sure your output stage is configured properly to be able to correctly generate 576i. The TPG data will be a lot easier to debug using chipscope than image data.

 

Edit:

 

Now that I look at your block diagram more closely, you should not be driving our output video interface from the vtiming interface of the vid2axis core; that's supposed to go to a VTC detector.

 

I'd recommend to start with this:

TPG -> VDMA -> AXIS2Vid

 

where you have a VTC in generate-only mode configured to generate 576i and connected to the AXIS2Vid.

www.xilinx.com
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Anonymous
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Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

Thank you.

 

Let me give you a background of our issue:

 

Yes, initially that's what we had, all sync signals were being generated from VTC (generator, 576i). Since we could not get the required output (we noticed that in the output of VTC generator (576i), whenever the VSYNC signal went low, at the same instant, HSYNC signal went low too, which always generates the odd field according to PAL encoder ADV7392 Figure 112. SD Timing Mode 2, Slave Option, PAL) The condition for even field was never met (when viewed on ILA). In order to sort out this issue, we are adding one block at a time and trying to figure out where the problem lies. I hope we are taking the right method to solve this. All of the recent questions I have posted on this forum are with respect to this same issue.

 

Back to the question above,

 

1. Using TPG, how can I generate the interlaced video? Output will be progressive, right? Will it be of help in this case? Ultimately, my input video will be interlaced. Since I am primarily facing an issue due to interlaced video support, should I still go ahead and try with a TPG?

 

2. Also could you tell me the configurations which should be used for VDMA in this case? Considering PAL resolution (total frame size is 864 X 625 including sync and blank; active is 720 X 576; interlaced)

 

I would like to add these points:

 

3. To make sure that decoder and encoder interface is working I have connected the output of decoder(tvp5150) directly to encoder input(adv7392) interlaced format..here I have observed that the video from pal camera is displayed on monitor clearly without distortion in any of the modes of operation.

 

4.Since the video was clear I then added only video in stream out block between pal  decoder and encoder. The output video on monitor was black completely. For this when checked on ILA probe output from video -in-axis out was zero.So I then added vdma in the path as mentioned earlier in my design.Now the output  is stable with a vertical black band  in the video with distortion at the borders.So I added vtc(version 6.1) in detection mode with interlaced video support.

 

what am I missing here? does video in stream out block support interlaced video?even after connecting sync signals from vtc with generator enabled the video doesnot seem to change..

is there something missing in the design?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-31-2012

Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

Hi,

Looks like there is no field id information being passed from the vid_in to axi4 module to the video output.
Thanks,
Anirudh

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Anonymous
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Re: Interlaced Video: 576i; Issue with VideoInAXISout block's output

@athandr @bwiec

 

Thank you for your response. We have already tried feeding FID to vid_in to axi4 module. It does not create any difference in the output signals.

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