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Anonymous
Not applicable
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Interlaced Video: VDMA Configuration

I have the following queries regarding interlaced video (PAL: 576i):

 

1. I want to know the VDMA configurations for interlaced video. Currently, this is what I'm doing on Vivado:

 

 

 

configuration on SDK looks like this:

 

 {
    status = *(vdma_addr+0x4/4);
    *(vdma_addr+0x0/4) = 0x8003;
    *(vdma_addr+0x54/4) = 720;
    *(vdma_addr+0x58/4) = 720;
    *(vdma_addr+0x5C/4) = 0x13000000;
    *(vdma_addr+0x60/4) = 0x13000000;
    *(vdma_addr+0x64/4) = 0x13000000;
    *(vdma_addr+0x50/4) = 288;
 }

 

These configurations output a video as shown here.

 

Please note that I have come across this question.

 

2. I have noticed that sometimes, VideoToAXI4S block outputs data = 0 sometimes. Here is what I did:
For a particular design on Vivado, I used to get an output video (as in point #1 above). Next, to analyze waveforms, in "Set-Up-Debug", I increased the "Sample of Data Depth" parameter from 1024 to 16384 (Note that I had not changed anything else). I implemented the design again and generated bit-stream. There was no output and when I saw the waveforms, the output of VideoToAXI4S block (data bits) was all zero. Why does this happen? The monitor was all black too.

 

 

 

 

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4 Replies
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Xilinx Employee
Xilinx Employee
6,335 Views
Registered: ‎08-02-2011

Re: Interlaced Video: VDMA Configuration

Hi Meghan,

 

The VDMA itself has no concept of interlaced vs progressive. So for a straight passthrough of interlaced data, you'll configure the VDMA just like normal but set the vsize to be the number of lines per field.

www.xilinx.com
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Anonymous
Not applicable
6,252 Views

Re: Interlaced Video: VDMA Configuration

Thank you. @bwiec

 

You mean the number of ACTIVE lines per field. Right?

 

Could you please comment on my 2nd doubt too?

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Xilinx Employee
Xilinx Employee
6,217 Views
Registered: ‎08-02-2011

Re: Interlaced Video: VDMA Configuration

Sure, Meghan.

 

Yes, I mean active lines.

 

Hmm well the first thing I'd do is run a reset_project tcl command to clean up all output products generated from vivado and re-run synth/impl just to make sure it's not some goofy tool issue.

 

After that, I'd take a look at timing. Depending on your device, 16K deep ILAs may use up a significant number of BRAMs on the device. This means timing will be harder to close and maybe that's the issue. Double check your timing report to make sure.

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Anonymous
Not applicable
6,198 Views

Re: Interlaced Video: VDMA Configuration

That helps! Thank you @bwiec

 

Another question:

1. Depending on what parameters should I configure the VideoInAXI4Sout block? Currently for PAL input video, I have 1 pixel per clock, 8 component width, mono/sensor format and fifo depth of 1024 (I have tried with 32 too...it's the same output video I get). Hysteresis level is 12. I am getting an output as shown here. I suspect it is because of Video-In-AXI4S-out block since this introduces certain delay in data transfer. However, the sync signals are generated by VTC towards the end of my processing......as input to AXI4S-in-Video-out block. Am I right?

 

screenshot.png

 

 

2. Basically, will this VTC generator generate sync signals considering the delay in data due to all other video processing blocks through with data passes to reach AXI4S-in-Video-out?

 

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