Intra-clock violation for clockoutphy_out in MIPI CSI-2 RX Subsystem IP in 2019.2

[thejashree_13]

Hello,

I am using MIPI CSI-2 RX Subsystem IP v4.1 in my design. The target device is xczu7cg-fbvb900-1-e. I am getting Intra-clock violation for the clockoutphy_out signal.

The IP is configured for 2500Mb/s line rate, 4 lanes and 4 pixels per clock. The lite_aclk is 100Mhz and video_aclk is 250Mhz.

Find the attached image for the timing details

Please find the attached files for TCL file for the block diagram and also find the .xci file for the MIPI CSI-2 RX Subsystem.

I am using the above clock in the design. But i am getting the intra clock violation for the same.Is there any way to get rid of this intra clock violation

With regards,

Thejashree

[karnanl · Accepted solution]

Hello @thejashree_13 

This is an expected result due to the speed file limitation for Vivado 2019.2. , MIPI IP implementation for UltraScale+ speed grade=-1 device is limited to 2400Mbps.
If you need to implement 2500Mbps with speed grade=-1, please migrate to Vivado 2020.1

Thanks & regards
Leo

[thejashree_13]

Hi @karnanl ,

Thank you so much for the response

With regards,

Thejashree