This may be possible, but more work than exporting the System Generator design. There would be several hurdles in trying to run hardware co-sim with a DDR controller (assuming you are using MIG):
1. There are particular constraints that you will need for the PHY interface (such as timing, IOStandard, etc). 2. There are particular synthesis / implementation options you should be using for the controller. 3. The timing parameters of the controller / memory part would need to be maintained.
The first two issues could have potential solutions with varying degrees of effort, but there is no direct flow for accomplishing this. The third issue would pose the biggest problem. Because of the timing parameters associated with the controller/memory part, single-stepped hardware co-sim would not work. You would need to use a free-running clock, but this has additional problems associated with it.
A simplier approach would be to write a synthesizable testbench that you could use to test the System Generator and DDR controller design.
One difficulty you'll likely encounter is that most memory controllers use bi-directional IO as well as multiple clocks on occasion. The SysGen HDL black box interface does not currently support bi-directional signals for top level ports and all clocks are driven by a single system clock.
As was pointed out, this type of complex HDL design is better suited for integration in ISE after you've generated the DSP portion of your design.