Is there a recommended DPHY chip suitable for 8-channel mipi CMOS?
Or can I connect two 5-channel DPHYs? Is the clock part connected together?
Any UltraScale+ device will do the job.
FYI,Xilinx MIPI D-PHY RX IP support 8-lane configuration. (See also PG202)But, you may need to use 3rd vendor MIPI CSI-2 RX core or design your own IP, since Xilinx MIPI CSI-2 RX Subsystem support max 4lane configuration only.