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filipozimek
Visitor
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Registered: ‎04-16-2018

Locking problem with AXI4-Stream to Video Out v4.0

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Hi!

 

I have created a small project to start with video. Please take a look at the diagram:

 

block_diagram.png

clk_wiz_0 generates 25.175 MHz from master clock. I wrote a simple test pattern generator which generated AXI4 video stream with proper marking of the EOL and SOF frames. My test unit generates video stream 800 by 525 px with three big horizontal stripes (x"FF0000", x"00FF00" and x"0000FF").  The Video Timing Controller v6.1 is configured to generate timings for 640x480p.

I have simulated that design but I don't see any activity on vid_vsync, vid_hsync, etc output and according to status bits the vtc core is in idle state. No overflow or underflow observed. This is my simulation:

 

 

sim.png

 

This project is published here: https://github.com/filipamator/v_axis_gen

The design files are here: https://github.com/filipamator/v_axis_gen/tree/master/v_axis_gen.srcs/sources_1/imports/axis-test

 

Does anybody know why AXI4-Stream to Video Out v4.0 is not able to lock to the incoming stream? I see some activity on vtg_ce output, so some kind of the feedback to vtc is present. How long it takes to lock vtc to incoming video stream?

 

Kind regards,

Filip.

 

1 Solution

Accepted Solutions
chrisar
Xilinx Employee
Xilinx Employee
2,606 Views
Registered: ‎08-01-2007

Make sure that you setup the AXI4-Stream to Video Out in the appropriate timing mode.  The different modes can be found documented in the AXI4-Stream to Video Out Product Guide PG044 under the Timing Modes section.


The locking time for the Video Timing Controller (VTC) is documented in the Video Timing Controller Product Guide PG016 under the LOCKED bit for the Detector Timing Status Register 0x0024.  The typical lock time is 3-5 frames.  But it should be noted that this is 3-5 consecutive frames.  If the AXI4-Stream to Video Out is in Slave Timing mode, where it keeps disabling the VTC to align the data it may take longer, as the VTC will need to be enabled for 3-5 consecutive frames before it will lock.

 

UPDATE:

I forgot to mention that your VTC needs to be configured for the same resolution as your Test Pattern Generator (TPG).  Based on your description, the VTC will never lock because the AXI4-Stream to Video Out core is will continue to pause the VTC as it tries to align the 800x255 frame to the 640x480 frame, which will keep it form locking.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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4 Replies
chrisar
Xilinx Employee
Xilinx Employee
2,607 Views
Registered: ‎08-01-2007

Make sure that you setup the AXI4-Stream to Video Out in the appropriate timing mode.  The different modes can be found documented in the AXI4-Stream to Video Out Product Guide PG044 under the Timing Modes section.


The locking time for the Video Timing Controller (VTC) is documented in the Video Timing Controller Product Guide PG016 under the LOCKED bit for the Detector Timing Status Register 0x0024.  The typical lock time is 3-5 frames.  But it should be noted that this is 3-5 consecutive frames.  If the AXI4-Stream to Video Out is in Slave Timing mode, where it keeps disabling the VTC to align the data it may take longer, as the VTC will need to be enabled for 3-5 consecutive frames before it will lock.

 

UPDATE:

I forgot to mention that your VTC needs to be configured for the same resolution as your Test Pattern Generator (TPG).  Based on your description, the VTC will never lock because the AXI4-Stream to Video Out core is will continue to pause the VTC as it tries to align the 800x255 frame to the 640x480 frame, which will keep it form locking.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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watari
Teacher
Teacher
2,203 Views
Registered: ‎06-16-2013

Hi @filipozimek

 

Here is helpful information for debugging your design.

Would you refer this information ?

 

- The meaning of status[31:0] signal

[0] | Idle state

[1] | Course Align, Wait for VTG SOF

[2] | Course Align, Wait for FIFO SOF

[3] | Fine Align, VTG EOL Leading

[4] | Fine Align, VTG EOL Lagging

[5] | Fine Align, VTG SOF Leading

[6] | Fine Align, VTG SOF Lagging

[7] | Fine Align Active

[8] | Fine Align Locked

[9] | Lost Align, VTG EOL Leading

[10] | Lost Align, VTG EOL Lagging

[11] | Lost Align, VTG SOF Leading

[12] | Lost Align, VTG SOF Lagging

[15:13] | N/A

[31:16] | VTG Lag. x[clk] delayed

 

---

 

In this case, you should add some delay at video control signal.

 

Best regards,

 

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filipozimek
Visitor
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Registered: ‎04-16-2018

Chrisar thank you for your answer, I changed my test pattern generator do generate appropriate stream (640x480) and I can get a lock to incoming video stream. 

I was pretty sure that video stream must contain blank data (full frame size for 640x480 would be 800x525).

I have attached results from my simulation - after ~90 ms 'locked' signal from Video Out IP core is asserted. This design works fine in my hardware (small Artix-7 35T with R-2R ladder as a DAC and VGA monitor).

 

 

vid_out_lock.png

florentw
Moderator
Moderator
2,190 Views
Registered: ‎11-09-2015

Hi @filipozimek,

 

I was pretty sure that video stream must contain blank data (full frame size for 640x480 would be 800x525).

> In the AXI4-Stream interface, there is no blanking data. It is only the active video.

 

Thank you for sharing your results. If everything is clear for you, please kindly mark @chrisar reply as accepted solution to close the topic.

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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