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Adventurer
Adventurer
598 Views
Registered: ‎06-20-2019

Low performance of VDMA-MiG bridge

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Hello,

I have been trying to resize an incoming video and I have to use PL DDR due to the specs. I am using an HLS based resize IP. The incoming frames are guided by VDMA to DDR4 memory. Then, I am reading it back with a lower frequency. (The frames are written to the memory at 148.5MHz and it is read by 74.25MHz)(I cannot change these frequency values btw, it is required for overall system to work). However, the frame I am getting is corrupted. You may see the images below and deduct some ideas about how it is corrupted. Since the frequency difference might be a problem, I have changed my way and tried to write and read a frame at the same frequency values(and deleted the resize ip). Yet, I am still seeing a corrupted video. When I have changed the interconnected from custom to high performance setting, the video became clearer but not enough(this made me believe that  the problem is due to low performance). Since read frequency is lower, I set the VDMA to read priority. However, after seeing that it didn't work, i tried the other arbitration options such as write priority, round robin etc. I know what they are but none of them gave me the needed performance. A guidance would be great at this moment since I tried almost everything I can.

The first image that you can see is my input.

First corrupted image shows you what kind of an image can be seen when I write and read at the same freq. value.

Second corrupted image shows you what kind of an image can be seen when my main system is working.

Thank you for your valuable time.

input_image.jpg
corrupted_im2.png
corrupted_im1.png
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Voyager
Voyager
400 Views
Registered: ‎03-28-2016

Re: Low performance of VDMA-MiG bridge

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@yhy.xilinx 

I would also recommend checking your VDMA settings.  Specifying the HSIZE in bytes is easy to mess up.  Also check the Stride value that you are using.  It is also specified in bytes.

Make sure that you are properly reformatting the video when you crop the image.  Make sure the Tuser and Tlast are correct for the cropped image.

I like to use a test pattern generator that outputs a ramp pattern so that it's easy to see the pattern when I look at the data stored in memory.  A test pattern like that is pretty easy to write for yourself.

I would recommend cutting the problem in half.  Load a test pattern into the DDR and then use the VDMA to read that image and display it.  Once that works you know the display section is good.  Provide a known pattern to the input section and check what gets written to memory.  Once that works you know the input section is good.  Then try running both sections together.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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7 Replies
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Mentor
Mentor
555 Views
Registered: ‎06-16-2013

Re: Low performance of VDMA-MiG bridge

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Hi @yhy.xilinx 

 

Did you set proper parameter on VDMA ?

Also, would you tell me bus width at AXI4 and DRAM and share the movie when it occurs ?

 

Best regards,

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Adventurer
Adventurer
546 Views
Registered: ‎06-20-2019

Re: Low performance of VDMA-MiG bridge

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Hi @watari,
I followed the "General Use Cases" section of the AXI VDMA document. I created a state machine to reach the registers with AXILite protocol and I confronted with no errors. Most of the time, when it flags an error, the data flow stops. However, I must say that AXI VDMA status registers are not showing me any error flags. Moreover, I have read the registers that are written and the data were written properly. Other than that, I enabled "allow unaligned transfer" option(DRE) for both sides(read and write). Memory Map Data Width(64) is more than Stream Data Width(32). I have tried various read and write data burst size combinations to get the proper output. Also, I have increased the line buffer depth to its higher value(16384). It was not working when it was 4096, too. I am using triple buffer mode and read channel(dynamic-slave) is free running while write channel is sync. in accordance with s2mm_tuser(dynamic-master).

There is an AXI interconnect between VDMA and MIG. "M_AXI_MM2S" and "M_AXI_S2MM" channels are directly connected to the S00_AXI and S01_AXI ports of interconnect, respectively. Their wdata/rdata is 64 bit width and awaddr/araddr is 32bit width. Interconnect has two slave, one master port(2:1). The master is connected to MIG whose araddr/awaddr is 30 bit width and rdata/wdata is 128 bit width.

Thank you very much for your answer.

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Mentor
Mentor
540 Views
Registered: ‎06-16-2013

Re: Low performance of VDMA-MiG bridge

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Hi @yhy.xilinx 

 

What memory device are you using ? How many device are you using ? What is dram clock frequency ?

Also, what is your target resolution ? FHD@60p ?

If yes, it might be band width issue.

I suggest you tochange buffer size on FIFO or line memory.

 

Best regards,

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Adventurer
Adventurer
530 Views
Registered: ‎06-20-2019

Re: Low performance of VDMA-MiG bridge

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Hi @watari,

I am using PL DDR4 which is an internal memory, not SODIMM, UDIMM or etc. When I add the MIG structure to my system and choose the option as ddr4 sdram, the IP customization window directly adjust the settings according to the DDR4 memory on the Ultrazed SOM card(it chooses the model). What I am trying to do is following, I am getting a video whose resolution is 1920x1080@60. However, due to the adjustments throughout my design, I am going to use 1280x720 portion of it. In other words, incoming 1920x1080 is cropped and the frame that is being guided to MIG via VDMA is 1280x720@148.5MHz. However, in order to display it, the frequency must be 74.25MHz. Therefore, I am reading it at 74.25MHz. By this means, I aimed not to use another async. buffer. Memory is written at 148.5MHz, it is read at 74.25MHz. It should act as a buffer.(by the way, I also tried to write and read 1920x1080@60 to MIG, it didn't work also. Yet, I think you are right about bandwidth. The reason is that when I wrote 1920x1080 and read it with directly with the same frequency, the output image I am observing is more corrupted(second image I added above). When I wrote 1280x720, it seems that it is more similar to the input(last image I added above)).

The DRAM frequency is 300MHz.PHY to controller is 4:1. I observed difference at the output video when I changed memory address map from Row bank coloumn to bank row coloumn. I think this is another sign about the problem.

I understand your suggestion but line buffer depth is at its highest value. No bigger value option is provided by AXI VDMA. Are you mentioning about something else that I couldn't understand? How am I supposed to increase the bandwidth? I am now investigating how to do it.

Kind regards

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Mentor
Mentor
478 Views
Registered: ‎06-16-2013

Re: Low performance of VDMA-MiG bridge

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Hi @yhy.xilinx 

 

Would you share your design or board design, if possible ?

At least, I suspect wrong parameter setting and wrong resolution to output video signal to monitor.

I guess it seems parameter issue.

 

Best regards,

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Moderator
Moderator
430 Views
Registered: ‎11-09-2015

Re: Low performance of VDMA-MiG bridge

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Hi @yhy.xilinx 

With the output I see, this is very likely that you have misconfigured the VDMA. I would check the HSIZE and the stride. Remember that these values have to be in number of bytes.

Also how do you know that this is not your HLS IP which is causing the issue?

You might want to add an ILA to check the data in and out of the AXI VMDA.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Highlighted
Voyager
Voyager
401 Views
Registered: ‎03-28-2016

Re: Low performance of VDMA-MiG bridge

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@yhy.xilinx 

I would also recommend checking your VDMA settings.  Specifying the HSIZE in bytes is easy to mess up.  Also check the Stride value that you are using.  It is also specified in bytes.

Make sure that you are properly reformatting the video when you crop the image.  Make sure the Tuser and Tlast are correct for the cropped image.

I like to use a test pattern generator that outputs a ramp pattern so that it's easy to see the pattern when I look at the data stored in memory.  A test pattern like that is pretty easy to write for yourself.

I would recommend cutting the problem in half.  Load a test pattern into the DDR and then use the VDMA to read that image and display it.  Once that works you know the display section is good.  Provide a known pattern to the input section and check what gets written to memory.  Once that works you know the input section is good.  Then try running both sections together.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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