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ww4u
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Visitor
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Registered: ‎06-10-2021

MIPI COMMAND and VIDEO mode can not switch

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Hi, we use MIPI DSI TX Subsystem in ZYNQ7, according to the PG238, it can change VIDEO and COMMAND mode freely by certain steps. However, we can change VIEDO mode to COMMAND, but can not change to VIDEO again.

In our system, we need to use the COMMAND mode to send the Long packets for configure the outer ic.

Thank you!

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karnanl
Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎03-30-2016

Hello @ww4u 

>We compare the REGs in normal VIDEO and after command->VIDEO, there is a difference in
>Interrupt Status Register (0x24) ,which is 1。

If Pixel Underrun occurs, you need to set "Core Enable" to 1->0->1
this will resetting all internal FIFOs and register.

>We found after change to COMMAND, the TIMMINGs is changed.

Hmm, MIPI DSI TX will not modify its TIMING registers.
Are you accidentally overwrite the TIMING registers value ? Could you please check your application program ?

1. Did you stop video input to MIPI DSI TX when you are using command mode ? ( If no, please do )
2. Could you please ensure that "Pixel data underrun" is not asserted ?
    Before re-send video data ?

Kind regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
452 Views
Registered: ‎03-30-2016

Hello @ww4u 

After you have finished sending long command,
1. Could you please share read all registers value and share it in this thread ?
2. Could you please share your steps to change mode (from Video -> Command) ?

REGS.png
Kind regards
Leo


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ww4u
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Registered: ‎06-10-2021

Thank you, we use the BSP to change mode, the snap is :

ww4u_0-1623407098076.png

 

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ww4u
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Visitor
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Registered: ‎06-10-2021

We verify the schedule by PG238 noted by you, the VIDEO&COMMAND change is same as the guide. 

The steps is:

  1. Power on
  2. Turn the xdsi and dphy 
  3. The video frame can be seen on the data line
  4. Change to command, send the commands, we can see the data changing on line.
  5. Change to video, the bus keep stable, can not see the video data.
  6.  
  7. to 
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ww4u
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Registered: ‎06-10-2021

We compare the REGs in normal VIDEO and after command->VIDEO, there is a difference in 

Interrupt Status Register (0x24) ,which is 1。

ww4u_0-1623416320620.png

Is this the reason for the VIDEO error? Related slutions?

 

ww4u
Visitor
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371 Views
Registered: ‎06-10-2021

We found after change to COMMAND, the TIMMINGs is changed. However, we set the TIMMINGs again before to VIDEO mode.

There is only a short frame on the data line. We guess the TIMMINGs are not be used. But we compare the REGs by reading, the values

are same. Have you get any suggesstions? Thank you!

ww4u
Visitor
Visitor
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Registered: ‎06-10-2021

 We captured the lane0 data, the follow is the correct frame

DS2_QuickPrint3.png

After change to command mode, change to video mode, there is a very short data on the line:

DS2_QuickPrint1.png

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karnanl
Xilinx Employee
Xilinx Employee
237 Views
Registered: ‎03-30-2016

Hello @ww4u 

>We compare the REGs in normal VIDEO and after command->VIDEO, there is a difference in
>Interrupt Status Register (0x24) ,which is 1。

If Pixel Underrun occurs, you need to set "Core Enable" to 1->0->1
this will resetting all internal FIFOs and register.

>We found after change to COMMAND, the TIMMINGs is changed.

Hmm, MIPI DSI TX will not modify its TIMING registers.
Are you accidentally overwrite the TIMING registers value ? Could you please check your application program ?

1. Did you stop video input to MIPI DSI TX when you are using command mode ? ( If no, please do )
2. Could you please ensure that "Pixel data underrun" is not asserted ?
    Before re-send video data ?

Kind regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

ww4u
Visitor
Visitor
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Registered: ‎06-10-2021
  • Yes, we found that after disable the edsi core, the TIMMING regs will be changed by some thing.
  • So we write back the TIMMING regs before enable the core
  • The steps we use now can work correctly:
    • disable the video stream
    • disable the core
    • to command
    • enable core
    • disable the core
    • to video
    • write back TIMMING regs
    • enable the core
    • enable the video stream
karnanl
Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎03-30-2016

Hello @ww4u 

Thanks for your update. Glad to know that MIPI DSI TX can work as expected.

>Yes, we found that after disable the edsi core, the TIMMING regs will be changed by some thing.

This is expected as mentioned in PG238.
Core disable/enable will reset also reset registers.
also_reset_registers.png

Kind regards
Leo


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