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msapunga
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Registered: ‎05-21-2021

MIPI CSI-2 RX Subsystem Dynamic Pixel format

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Hi,

I am looking into supporting different pixel formats for an implementation of a MIPI receiver. Does the MIPI RX IP for Ultrascale+ MPSOC support designs where we can dynamically change the pixel format (for example, changing from RAW12 to RAW8) on Vivado 2020.1?

Mark

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karnanl
Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @msapunga 
# Just adding my two cents.

If your sensor is sending multiple data-types (or pixel formats),
You can also generate MIPI CSI-2 RX Subsystem with VFB disable setting.

With VFB disabled , you will have a fixed 32 bit for video_out_tdata output signal.

MIPI_CSI2_RX_with_VFB_off.png

This IP will not do pixel/byte unpacking for you, so you need to unpack the byte data with a custom logic.
For more detailed info on how to do byte unpack, please see also MIPI CSI-2 RX chapter 11 "Data Format".

MIPI_CSI2_Unpacking_method_in_the_spec.png

Regards
Leo


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4 Replies
bpatil
Xilinx Employee
Xilinx Employee
369 Views
Registered: ‎03-07-2018

Hi @msapunga 

We cannot change Pixel Format of Xilinx MIPI CSI-2 RX SS IP dynamically during runtime. 

Once we setup in Configuration GUI it remains fixed. 

Regards,
Bhushan

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msapunga
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Registered: ‎05-21-2021

Hi @bpatil

Thanks for answering. If you will, may I know the reasons why this can't be done? Is there another way to get around this?

bpatil
Xilinx Employee
Xilinx Employee
314 Views
Registered: ‎03-07-2018

Hi @msapunga 

Main reason this is not possible because, currently this feature is not available in Xilinx MIPI CSI-2 RX SS IP and adding this feature will require significant efforts in current MIPI IP 

Workaround I can think of is using multiple bitstreams with multiboot or Partial reconfiguration. 

https://www.xilinx.com/support/documentation/application_notes/xapp1257-multiboot-fallback-spi-flash.pdf 

https://www.xilinx.com/support/documentation/application_notes/xapp1296-multiboot-fallback-icap.pdf 

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
karnanl
Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎03-30-2016

Hello @msapunga 
# Just adding my two cents.

If your sensor is sending multiple data-types (or pixel formats),
You can also generate MIPI CSI-2 RX Subsystem with VFB disable setting.

With VFB disabled , you will have a fixed 32 bit for video_out_tdata output signal.

MIPI_CSI2_RX_with_VFB_off.png

This IP will not do pixel/byte unpacking for you, so you need to unpack the byte data with a custom logic.
For more detailed info on how to do byte unpack, please see also MIPI CSI-2 RX chapter 11 "Data Format".

MIPI_CSI2_Unpacking_method_in_the_spec.png

Regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post